arch/arm/boot/dts/imx6qdl-icore.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR X11
   2 /*
   3  * Copyright (C) 2016 Amarula Solutions B.V.
   4  * Copyright (C) 2016 Engicam S.r.l.
   5  */
   6
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/input/input.h>
   9 #include <dt-bindings/sound/fsl-imx-audmux.h>
  10
  11 / {
  12         memory@10000000 {
  13                 device_type = "memory";
  14                 reg = <0x10000000 0x80000000>;
  15         };
  16
  17         chosen {
  18                 stdout-path = &uart4;
  19         };
  20
  21         backlight_lvds: backlight-lvds {
  22                 compatible = "pwm-backlight";
  23                 pwms = <&pwm3 0 100000>;
  24                 brightness-levels = <0 4 8 16 32 64 128 255>;
  25                 default-brightness-level = <7>;
  26         };
  27
  28         reg_1p8v: regulator-1p8v {
  29                 compatible = "regulator-fixed";
  30                 regulator-name = "1P8V";
  31                 regulator-min-microvolt = <1800000>;
  32                 regulator-max-microvolt = <1800000>;
  33                 regulator-boot-on;
  34                 regulator-always-on;
  35         };
  36
  37         reg_2p5v: regulator-2p5v {
  38                 compatible = "regulator-fixed";
  39                 regulator-name = "2P5V";
  40                 regulator-min-microvolt = <2500000>;
  41                 regulator-max-microvolt = <2500000>;
  42                 regulator-boot-on;
  43                 regulator-always-on;
  44         };
  45
  46         reg_3p3v: regulator-3p3v {
  47                 compatible = "regulator-fixed";
  48                 regulator-name = "3P3V";
  49                 regulator-min-microvolt = <3300000>;
  50                 regulator-max-microvolt = <3300000>;
  51                 regulator-boot-on;
  52                 regulator-always-on;
  53         };
  54
  55         reg_usb_h1_vbus: regulator-usb-h1-vbus {
  56                 compatible = "regulator-fixed";
  57                 regulator-name = "usb_h1_vbus";
  58                 regulator-min-microvolt = <5000000>;
  59                 regulator-max-microvolt = <5000000>;
  60                 regulator-boot-on;
  61                 regulator-always-on;
  62         };
  63
  64         reg_usb_otg_vbus: regulator-usb-otg-vbus {
  65                 compatible = "regulator-fixed";
  66                 regulator-name = "usb_otg_vbus";
  67                 regulator-min-microvolt = <5000000>;
  68                 regulator-max-microvolt = <5000000>;
  69                 regulator-boot-on;
  70                 regulator-always-on;
  71         };
  72
  73         rmii_clk: clock-rmii-clk {
  74                 compatible = "fixed-clock";
  75                 #clock-cells = <0>;
  76                 clock-frequency = <25000000>;  /* 25MHz for example */
  77         };
  78
  79         sound {
  80                 compatible = "simple-audio-card";
  81                 simple-audio-card,name = "imx6qdl-icore-sgtl5000";
  82                 simple-audio-card,format = "i2s";
  83                 simple-audio-card,bitclock-master = <&dailink_master>;
  84                 simple-audio-card,frame-master = <&dailink_master>;
  85                 simple-audio-card,widgets =
  86                         "Microphone", "Mic Jack",
  87                         "Headphone", "Headphone Jack",
  88                         "Line", "Line In Jack",
  89                         "Speaker", "Line Out Jack",
  90                         "Speaker", "Ext Spk";
  91                 simple-audio-card,routing =
  92                         "MIC_IN", "Mic Jack",
  93                         "Mic Jack", "Mic Bias",
  94                         "Headphone Jack", "HP_OUT";
  95
  96                 simple-audio-card,cpu {
  97                         sound-dai = <&ssi1>;
  98                 };
  99
 100                 dailink_master: simple-audio-card,codec {
 101                         sound-dai = <&sgtl5000>;
 102                 };
 103         };
 104 };
 105
 106 &audmux {
 107         pinctrl-names = "default";
 108         pinctrl-0 = <&pinctrl_audmux>;
 109         status = "okay";
 110
 111
 112         audmux_ssi1 {
 113                 fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
 114                 fsl,port-config = <
 115                         (IMX_AUDMUX_V2_PTCR_TFSDIR |
 116                         IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) |
 117                         IMX_AUDMUX_V2_PTCR_TCLKDIR |
 118                         IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) |
 119                         IMX_AUDMUX_V2_PTCR_SYN)
 120                         IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4)
 121                 >;
 122         };
 123
 124         audmux_aud4 {
 125                 fsl,audmux-port = <MX51_AUDMUX_PORT4>;
 126                 fsl,port-config = <
 127                         IMX_AUDMUX_V2_PTCR_SYN
 128                         IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
 129                 >;
 130         };
 131 };
 132
 133 &can1 {
 134         pinctrl-names = "default";
 135         pinctrl-0 = <&pinctrl_flexcan1>;
 136         xceiver-supply = <&reg_3p3v>;
 137 };
 138
 139 &can2 {
 140         pinctrl-names = "default";
 141         pinctrl-0 = <&pinctrl_flexcan2>;
 142         xceiver-supply = <&reg_3p3v>;
 143 };
 144
 145 &clks {
 146         assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
 147         assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
 148 };
 149
 150 &fec {
 151         pinctrl-names = "default";
 152         pinctrl-0 = <&pinctrl_enet>;
 153         phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
 154         clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
 155         phy-mode = "rmii";
 156         status = "okay";
 157 };
 158
 159 &gpmi {
 160         pinctrl-names = "default";
 161         pinctrl-0 = <&pinctrl_gpmi_nand>;
 162         nand-on-flash-bbt;
 163         status = "okay";
 164 };
 165
 166 &i2c1 {
 167         clock-frequency = <100000>;
 168         pinctrl-names = "default";
 169         pinctrl-0 = <&pinctrl_i2c1>;
 170         status = "okay";
 171 };
 172
 173 &i2c2 {
 174         clock-frequency = <100000>;
 175         pinctrl-names = "default";
 176         pinctrl-0 = <&pinctrl_i2c2>;
 177         status = "okay";
 178 };
 179
 180 &i2c3 {
 181         clock-frequency = <100000>;
 182         pinctrl-names = "default";
 183         pinctrl-0 = <&pinctrl_i2c3>;
 184         status = "okay";
 185
 186         ov5640: camera@3c {
 187                 compatible = "ovti,ov5640";
 188                 pinctrl-names = "default";
 189                 pinctrl-0 = <&pinctrl_ov5640>;
 190                 reg = <0x3c>;
 191                 clocks = <&clks IMX6QDL_CLK_CKO>;
 192                 clock-names = "xclk";
 193                 DOVDD-supply = <&reg_1p8v>;
 194                 AVDD-supply = <&reg_3p3v>;
 195                 DVDD-supply = <&reg_3p3v>;
 196                 powerdown-gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>;
 197                 reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>;
 198                 status = "disabled";
 199
 200                 port {
 201                         ov5640_to_mipi_csi2: endpoint {
 202                                 remote-endpoint = <&mipi_csi2_in>;
 203                                 clock-lanes = <0>;
 204                                 data-lanes = <1 2>;
 205                         };
 206                 };
 207         };
 208
 209         sgtl5000: codec@a {
 210                 #sound-dai-cells = <0>;
 211                 compatible = "fsl,sgtl5000";
 212                 reg = <0x0a>;
 213                 clocks = <&clks IMX6QDL_CLK_CKO>;
 214                 VDDA-supply = <&reg_2p5v>;
 215                 VDDIO-supply = <&reg_3p3v>;
 216                 VDDD-supply = <&reg_1p8v>;
 217         };
 218 };
 219
 220 &mipi_csi {
 221         status = "disabled";
 222
 223         port@0 {
 224                 reg = <0>;
 225
 226                 mipi_csi2_in: endpoint {
 227                         remote-endpoint = <&ov5640_to_mipi_csi2>;
 228                         clock-lanes = <0>;
 229                         data-lanes = <1 2>;
 230                 };
 231         };
 232 };
 233
 234 &pwm3 {
 235         pinctrl-names = "default";
 236         pinctrl-0 = <&pinctrl_pwm3>;
 237         status = "okay";
 238 };
 239
 240 &ssi1 {
 241         fsl,mode = "i2s-slave";
 242         status = "okay";
 243 };
 244
 245 &uart4 {
 246         pinctrl-names = "default";
 247         pinctrl-0 = <&pinctrl_uart4>;
 248         status = "okay";
 249 };
 250
 251 &usbh1 {
 252         vbus-supply = <&reg_usb_h1_vbus>;
 253         disable-over-current;
 254         status = "okay";
 255 };
 256
 257 &usbotg {
 258         vbus-supply = <&reg_usb_otg_vbus>;
 259         pinctrl-names = "default";
 260         pinctrl-0 = <&pinctrl_usbotg>;
 261         disable-over-current;
 262         status = "okay";
 263 };
 264
 265 &usdhc1 {
 266         pinctrl-names = "default";
 267         pinctrl-0 = <&pinctrl_usdhc1>;
 268         cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 269         no-1-8-v;
 270         status = "okay";
 271 };
 272
 273 &usdhc3 {
 274         pinctrl-names = "default";
 275         pinctrl-0 = <&pinctrl_usdhc3>;
 276         no-1-8-v;
 277         non-removable;
 278         status = "disabled";
 279 };
 280
 281 &iomuxc {
 282         pinctrl_audmux: audmuxgrp {
 283                 fsl,pins = <
 284                         MX6QDL_PAD_DISP0_DAT20__AUD4_TXC  0x130b0
 285                         MX6QDL_PAD_DISP0_DAT21__AUD4_TXD  0x110b0
 286                         MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
 287                         MX6QDL_PAD_DISP0_DAT23__AUD4_RXD  0x130b0
 288                 >;
 289         };
 290
 291         pinctrl_enet: enetgrp {
 292                 fsl,pins = <
 293                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x1b0b0
 294                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x1b0b1
 295                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 296                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x1b0b0
 297                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x1b0b0
 298                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x1b0b0
 299                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x1b0b0
 300                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 301                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 302                         MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23     0x1b0b0
 303                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x1b0b0
 304                 >;
 305         };
 306
 307         pinctrl_flexcan1: flexcan1grp {
 308                 fsl,pins = <
 309                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020
 310                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b020
 311                 >;
 312         };
 313
 314         pinctrl_flexcan2: flexcan2grp {
 315                 fsl,pins = <
 316                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b020
 317                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b020
 318                 >;
 319         };
 320
 321         pinctrl_gpmi_nand: gpminandgrp {
 322                 fsl,pins = <
 323                         MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
 324                         MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
 325                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
 326                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
 327                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
 328                         MX6QDL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
 329                         MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
 330                         MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
 331                         MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
 332                         MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
 333                         MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
 334                         MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
 335                         MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
 336                         MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
 337                         MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
 338                         MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
 339                         MX6QDL_PAD_SD4_DAT0__NAND_DQS      0x00b1
 340                 >;
 341         };
 342
 343         pinctrl_i2c1: i2c1grp {
 344                 fsl,pins = <
 345                         MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
 346                         MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
 347                 >;
 348         };
 349
 350         pinctrl_i2c2: i2c2grp {
 351                 fsl,pins = <
 352                         MX6QDL_PAD_EIM_EB2__I2C2_SCL  0x4001b8b1
 353                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
 354                 >;
 355         };
 356
 357         pinctrl_i2c3: i2c3grp {
 358                 fsl,pins = <
 359                         MX6QDL_PAD_GPIO_5__I2C3_SCL  0x4001b8b1
 360                         MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 361                 >;
 362         };
 363
 364         pinctrl_ov5640: ov5640grp {
 365                 fsl,pins = <
 366                         MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b0
 367                         MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0
 368                         MX6QDL_PAD_GPIO_0__CCM_CLKO1      0x130b0
 369                 >;
 370         };
 371
 372         pinctrl_uart4: uart4grp {
 373                 fsl,pins = <
 374                         MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
 375                         MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
 376                 >;
 377         };
 378
 379         pinctrl_pwm3: pwm3grp {
 380                 fsl,pins = <
 381                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
 382                 >;
 383         };
 384
 385         pinctrl_usbotg: usbotggrp {
 386                 fsl,pins = <
 387                         MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
 388                 >;
 389         };
 390
 391         pinctrl_usdhc1: usdhc1grp {
 392                 fsl,pins = <
 393                         MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17070
 394                         MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10070
 395                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17070
 396                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17070
 397                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17070
 398                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070
 399                 >;
 400         };
 401
 402         pinctrl_usdhc3: usdhc3grp {
 403                 fsl,pins = <
 404                         MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17059
 405                         MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10059
 406                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
 407                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
 408                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
 409                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
 410                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
 411                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
 412                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
 413                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
 414                 >;
 415         };
 416 };