arch/arm/boot/dts/dra72-evm-revc.dts

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
   4  */
   5 #include "dra72-evm-common.dtsi"
   6 #include "dra72x-mmc-iodelay.dtsi"
   7 #include <dt-bindings/net/ti-dp83867.h>
   8
   9 / {
  10         model = "TI DRA722 Rev C EVM";
  11
  12         memory@0 {
  13                 device_type = "memory";
  14                 reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
  15         };
  16
  17         evm_1v8_sw: fixedregulator-evm_1v8 {
  18                 compatible = "regulator-fixed";
  19                 regulator-name = "evm_1v8";
  20                 regulator-min-microvolt = <1800000>;
  21                 regulator-max-microvolt = <1800000>;
  22                 vin-supply = <&smps4_reg>;
  23                 regulator-always-on;
  24                 regulator-boot-on;
  25         };
  26 };
  27
  28 &i2c1 {
  29         tps65917: tps65917@58 {
  30                 reg = <0x58>;
  31
  32                 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
  33         };
  34 };
  35
  36 #include "dra72-evm-tps65917.dtsi"
  37
  38 &ldo2_reg {
  39         /* LDO2_OUT --> VDDA_1V8_PHY2 */
  40         regulator-always-on;
  41         regulator-boot-on;
  42 };
  43
  44 &hdmi {
  45         vdda-supply = <&ldo2_reg>;
  46 };
  47
  48 &pcf_gpio_21 {
  49         interrupt-parent = <&gpio3>;
  50         interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
  51 };
  52
  53 &mac {
  54         mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
  55                      <&pcf_hdmi 9 GPIO_ACTIVE_LOW>,     /* P11 */
  56                      <&pcf_hdmi 10 GPIO_ACTIVE_LOW>;    /* P12 */
  57         dual_emac;
  58 };
  59
  60 &cpsw_emac0 {
  61         phy-handle = <&dp83867_0>;
  62         phy-mode = "rgmii-id";
  63         dual_emac_res_vlan = <1>;
  64 };
  65
  66 &cpsw_emac1 {
  67         phy-handle = <&dp83867_1>;
  68         phy-mode = "rgmii-id";
  69         dual_emac_res_vlan = <2>;
  70 };
  71
  72 &davinci_mdio {
  73         dp83867_0: ethernet-phy@2 {
  74                 reg = <2>;
  75                 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
  76                 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
  77                 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
  78                 ti,min-output-impedance;
  79                 interrupt-parent = <&gpio6>;
  80                 interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
  81                 ti,dp83867-rxctrl-strap-quirk;
  82         };
  83
  84         dp83867_1: ethernet-phy@3 {
  85                 reg = <3>;
  86                 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
  87                 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
  88                 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
  89                 ti,min-output-impedance;
  90                 interrupt-parent = <&gpio6>;
  91                 interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
  92                 ti,dp83867-rxctrl-strap-quirk;
  93         };
  94 };
  95
  96 &mmc1 {
  97         pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
  98         pinctrl-0 = <&mmc1_pins_default>;
  99         pinctrl-1 = <&mmc1_pins_hs>;
 100         pinctrl-2 = <&mmc1_pins_sdr12>;
 101         pinctrl-3 = <&mmc1_pins_sdr25>;
 102         pinctrl-4 = <&mmc1_pins_sdr50>;
 103         pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
 104         pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
 105         vqmmc-supply = <&ldo1_reg>;
 106 };
 107
 108 &mmc2 {
 109         pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
 110         pinctrl-0 = <&mmc2_pins_default>;
 111         pinctrl-1 = <&mmc2_pins_hs>;
 112         pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
 113         pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
 114         vmmc-supply = <&evm_1v8_sw>;
 115 };