1 menu "ARM architecture"
10 select SYS_CACHE_SHIFT_6
13 config POSITION_INDEPENDENT
14 bool "Generate position-independent pre-relocation code"
15 select INIT_SP_RELATIVE
17 U-Boot expects to be linked to a specific hard-coded address, and to
18 be loaded to and run from that address. This option lifts that
19 restriction, thus allowing the code to be loaded to and executed
20 from almost any address. This logic relies on the relocation
21 information that is embedded in the binary to support U-Boot
22 relocating itself to the top-of-RAM later during execution.
24 config INIT_SP_RELATIVE
25 bool "Specify the early stack pointer relative to the .bss section"
27 U-Boot typically uses a hard-coded value for the stack pointer
28 before relocation. Enable this option to instead calculate the
29 initial SP at run-time. This is useful to avoid hard-coding addresses
30 into U-Boot, so that it can be loaded and executed at arbitrary
31 addresses and thus avoid using arbitrary addresses at runtime.
33 If this option is enabled, the early stack pointer is set to
34 &_bss_start with a offset value added. The offset is specified by
35 SYS_INIT_SP_BSS_OFFSET.
37 config SYS_INIT_SP_BSS_OFFSET
38 int "Early stack offset from the .bss base address"
39 depends on INIT_SP_RELATIVE
42 This option's value is the offset added to &_bss_start in order to
43 calculate the stack pointer. This offset should be large enough so
44 that the early malloc region, global data (gd), and early stack usage
45 do not overlap any appended DTB.
47 config LINUX_KERNEL_IMAGE_HEADER
50 Place a Linux kernel image header at the start of the U-Boot binary.
51 The format of the header is described in the Linux kernel source at
52 Documentation/arm64/booting.txt. This feature is useful since the
53 image header reports the amount of memory (BSS and similar) that
54 U-Boot needs to use, but which isn't part of the binary.
56 if LINUX_KERNEL_IMAGE_HEADER
57 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
60 The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
61 TEXT_OFFSET value written to the Linux kernel image header.
68 ARM GICV3 Interrupt translation service (ITS).
69 Basic support for programming locality specific peripheral
70 interrupts (LPI) configuration tables and enable LPI tables.
71 LPI configuration table can be used by u-boot or Linux.
72 ARM GICV3 has limitation, once the LPI table is enabled, LPI
73 configuration table can not be re-programmed, unless GICV3 reset.
77 default y if ARM64 && !POSITION_INDEPENDENT
79 config DMA_ADDR_T_64BIT
89 # Used for compatibility with asm files copied from the kernel
90 config ARM_ASM_UNIFIED
94 # Used for compatibility with asm files copied from the kernel
99 bool "Do not enable icache"
102 Do not enable instruction cache in U-Boot.
104 config SPL_SYS_ICACHE_OFF
105 bool "Do not enable icache in SPL"
107 default SYS_ICACHE_OFF
109 Do not enable instruction cache in SPL.
111 config SYS_DCACHE_OFF
112 bool "Do not enable dcache"
115 Do not enable data cache in U-Boot.
117 config SPL_SYS_DCACHE_OFF
118 bool "Do not enable dcache in SPL"
120 default SYS_DCACHE_OFF
122 Do not enable data cache in SPL.
124 config SYS_ARM_CACHE_CP15
125 bool "CP15 based cache enabling support"
127 Select this if your processor suports enabling caches by using
131 bool "MMU-based Paged Memory Management Support"
132 select SYS_ARM_CACHE_CP15
134 Select if you want MMU-based virtualised addressing space
135 support via paged memory management.
138 bool 'Use the ARM v7 PMSA Compliant MPU'
140 Some ARM systems without an MMU have instead a Memory Protection
141 Unit (MPU) that defines the type and permissions for regions of
143 If your CPU has an MPU then you should choose 'y' here unless you
144 know that you do not want to use the MPU.
146 # If set, the workarounds for these ARM errata are applied early during U-Boot
147 # startup. Note that in general these options force the workarounds to be
148 # applied; no CPU-type/version detection exists, unlike the similar options in
149 # the Linux kernel. Do not set these options unless they apply! Also note that
150 # the following can be machine-specific errata. These do have ability to
151 # provide rudimentary version and machine-specific checks, but expect no
153 # CONFIG_ARM_ERRATA_430973
154 # CONFIG_ARM_ERRATA_454179
155 # CONFIG_ARM_ERRATA_621766
156 # CONFIG_ARM_ERRATA_798870
157 # CONFIG_ARM_ERRATA_801819
158 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
159 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
161 config ARM_ERRATA_430973
164 config ARM_ERRATA_454179
167 config ARM_ERRATA_621766
170 config ARM_ERRATA_716044
173 config ARM_ERRATA_725233
176 config ARM_ERRATA_742230
179 config ARM_ERRATA_743622
182 config ARM_ERRATA_751472
185 config ARM_ERRATA_761320
188 config ARM_ERRATA_773022
191 config ARM_ERRATA_774769
194 config ARM_ERRATA_794072
197 config ARM_ERRATA_798870
200 config ARM_ERRATA_801819
203 config ARM_ERRATA_826974
206 config ARM_ERRATA_828024
209 config ARM_ERRATA_829520
212 config ARM_ERRATA_833069
215 config ARM_ERRATA_833471
218 config ARM_ERRATA_845369
221 config ARM_ERRATA_852421
224 config ARM_ERRATA_852423
227 config ARM_ERRATA_855873
230 config ARM_CORTEX_A8_CVE_2017_5715
233 config ARM_CORTEX_A15_CVE_2017_5715
238 select SYS_CACHE_SHIFT_5
243 select SYS_CACHE_SHIFT_5
248 select SYS_CACHE_SHIFT_5
253 select SYS_CACHE_SHIFT_5
258 select SYS_CACHE_SHIFT_5
264 select SYS_CACHE_SHIFT_5
271 select SYS_CACHE_SHIFT_6
278 select SYS_CACHE_SHIFT_5
279 select SYS_THUMB_BUILD
285 select SYS_ARM_CACHE_CP15
287 select SYS_CACHE_SHIFT_6
291 select SYS_CACHE_SHIFT_5
296 select SYS_CACHE_SHIFT_5
300 default "arm720t" if CPU_ARM720T
301 default "arm920t" if CPU_ARM920T
302 default "arm926ejs" if CPU_ARM926EJS
303 default "arm946es" if CPU_ARM946ES
304 default "arm1136" if CPU_ARM1136
305 default "arm1176" if CPU_ARM1176
306 default "armv7" if CPU_V7A
307 default "armv7" if CPU_V7R
308 default "armv7m" if CPU_V7M
309 default "pxa" if CPU_PXA
310 default "sa1100" if CPU_SA1100
311 default "armv8" if ARM64
315 default 4 if CPU_ARM720T
316 default 4 if CPU_ARM920T
317 default 5 if CPU_ARM926EJS
318 default 5 if CPU_ARM946ES
319 default 6 if CPU_ARM1136
320 default 6 if CPU_ARM1176
325 default 4 if CPU_SA1100
328 config SYS_CACHE_SHIFT_5
331 config SYS_CACHE_SHIFT_6
334 config SYS_CACHE_SHIFT_7
337 config SYS_CACHELINE_SIZE
339 default 128 if SYS_CACHE_SHIFT_7
340 default 64 if SYS_CACHE_SHIFT_6
341 default 32 if SYS_CACHE_SHIFT_5
344 prompt "Select the ARM data write cache policy"
345 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
346 TARGET_BCMNSP || CPU_PXA || RZA1
347 default SYS_ARM_CACHE_WRITEBACK
349 config SYS_ARM_CACHE_WRITEBACK
350 bool "Write-back (WB)"
352 A write updates the cache only and marks the cache line as dirty.
353 External memory is updated only when the line is evicted or explicitly
356 config SYS_ARM_CACHE_WRITETHROUGH
357 bool "Write-through (WT)"
359 A write updates both the cache and the external memory system.
360 This does not mark the cache line as dirty.
362 config SYS_ARM_CACHE_WRITEALLOC
363 bool "Write allocation (WA)"
365 A cache line is allocated on a write miss. This means that executing a
366 store instruction on the processor might cause a burst read to occur.
367 There is a linefill to obtain the data for the cache line, before the
372 bool "Enable ARCH_CPU_INIT"
374 Some architectures require a call to arch_cpu_init().
375 Say Y here to enable it
377 config SYS_ARCH_TIMER
378 bool "ARM Generic Timer support"
379 depends on CPU_V7A || ARM64
382 The ARM Generic Timer (aka arch-timer) provides an architected
383 interface to a timer source on an SoC.
384 It is mandatory for ARMv8 implementation and widely available
388 bool "Support for ARM SMC Calling Convention (SMCCC)"
389 depends on CPU_V7A || ARM64
392 Say Y here if you want to enable ARM SMC Calling Convention.
393 This should be enabled if U-Boot needs to communicate with system
394 firmware (for example, PSCI) according to SMCCC.
397 bool "support boot from semihosting"
399 In emulated environments, semihosting is a way for
400 the hosted environment to call out to the emulator to
401 retrieve files from the host machine.
403 config SYS_THUMB_BUILD
404 bool "Build U-Boot using the Thumb instruction set"
407 Use this flag to build U-Boot using the Thumb instruction set for
408 ARM architectures. Thumb instruction set provides better code
409 density. For ARM architectures that support Thumb2 this flag will
410 result in Thumb2 code generated by GCC.
412 config SPL_SYS_THUMB_BUILD
413 bool "Build SPL using the Thumb instruction set"
414 default y if SYS_THUMB_BUILD
415 depends on !ARM64 && SPL
417 Use this flag to build SPL using the Thumb instruction set for
418 ARM architectures. Thumb instruction set provides better code
419 density. For ARM architectures that support Thumb2 this flag will
420 result in Thumb2 code generated by GCC.
422 config TPL_SYS_THUMB_BUILD
423 bool "Build TPL using the Thumb instruction set"
424 default y if SYS_THUMB_BUILD
425 depends on TPL && !ARM64
427 Use this flag to build TPL using the Thumb instruction set for
428 ARM architectures. Thumb instruction set provides better code
429 density. For ARM architectures that support Thumb2 this flag will
430 result in Thumb2 code generated by GCC.
433 config SYS_L2CACHE_OFF
436 If SoC does not support L2CACHE or one does not want to enable
437 L2CACHE, choose this option.
439 config ENABLE_ARM_SOC_BOOT0_HOOK
440 bool "prepare BOOT0 header"
442 If the SoC's BOOT0 requires a header area filled with (magic)
443 values, then choose this option, and create a file included as
444 <asm/arch/boot0.h> which contains the required assembler code.
446 config ARM_CORTEX_CPU_IS_UP
450 config USE_ARCH_MEMCPY
451 bool "Use an assembly optimized implementation of memcpy"
455 Enable the generation of an optimized version of memcpy.
456 Such an implementation may be faster under some conditions
457 but may increase the binary size.
459 config SPL_USE_ARCH_MEMCPY
460 bool "Use an assembly optimized implementation of memcpy for SPL"
461 default y if USE_ARCH_MEMCPY
462 depends on !ARM64 && SPL
464 Enable the generation of an optimized version of memcpy.
465 Such an implementation may be faster under some conditions
466 but may increase the binary size.
468 config TPL_USE_ARCH_MEMCPY
469 bool "Use an assembly optimized implementation of memcpy for TPL"
470 default y if USE_ARCH_MEMCPY
471 depends on !ARM64 && TPL
473 Enable the generation of an optimized version of memcpy.
474 Such an implementation may be faster under some conditions
475 but may increase the binary size.
477 config USE_ARCH_MEMSET
478 bool "Use an assembly optimized implementation of memset"
482 Enable the generation of an optimized version of memset.
483 Such an implementation may be faster under some conditions
484 but may increase the binary size.
486 config SPL_USE_ARCH_MEMSET
487 bool "Use an assembly optimized implementation of memset for SPL"
488 default y if USE_ARCH_MEMSET
489 depends on !ARM64 && SPL
491 Enable the generation of an optimized version of memset.
492 Such an implementation may be faster under some conditions
493 but may increase the binary size.
495 config TPL_USE_ARCH_MEMSET
496 bool "Use an assembly optimized implementation of memset for TPL"
497 default y if USE_ARCH_MEMSET
498 depends on !ARM64 && TPL
500 Enable the generation of an optimized version of memset.
501 Such an implementation may be faster under some conditions
502 but may increase the binary size.
504 config SET_STACK_SIZE
505 bool "Enable an option to set max stack size that can be used"
506 default y if ARCH_VERSAL || ARCH_ZYNQMP || ARCH_ZYNQ
508 This will enable an option to set max stack size that can be
512 hex "Define max stack size that can be used by U-Boot"
513 depends on SET_STACK_SIZE
514 default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP
515 default 0x1000000 if ARCH_ZYNQ
517 Define Max stack size that can be used by U-Boot so that the
518 initrd_high will be calculated as base stack pointer minus this
521 config ARM64_SUPPORT_AARCH32
522 bool "ARM64 system support AArch32 execution state"
524 default y if !TARGET_THUNDERX_88XX
526 This ARM64 system supports AArch32 execution state.
529 prompt "Target select"
534 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
536 config TARGET_EDB93XX
537 bool "Support edb93xx"
541 config TARGET_ASPENITE
542 bool "Support aspenite"
546 bool "Support gplugd"
554 Support for TI's DaVinci platform.
557 bool "Marvell Kirkwood"
558 select ARCH_MISC_INIT
559 select BOARD_EARLY_INIT_F
563 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
583 config TARGET_SPEAR300
584 bool "Support spear300"
585 select BOARD_EARLY_INIT_F
590 config TARGET_SPEAR310
591 bool "Support spear310"
592 select BOARD_EARLY_INIT_F
597 config TARGET_SPEAR320
598 bool "Support spear320"
599 select BOARD_EARLY_INIT_F
604 config TARGET_SPEAR600
605 bool "Support spear600"
606 select BOARD_EARLY_INIT_F
611 config TARGET_STV0991
612 bool "Support stv0991"
625 select BOARD_LATE_INIT
634 config TARGET_MX35PDK
635 bool "Support mx35pdk"
636 select BOARD_LATE_INIT
640 bool "Broadcom BCM283X family"
646 select SERIAL_SEARCH_ALL
651 bool "Broadcom BCM63158 family"
657 bool "Broadcom BCM68360 family"
663 bool "Broadcom BCM6858 family"
668 config TARGET_VEXPRESS_CA15_TC2
669 bool "Support vexpress_ca15_tc2"
671 select CPU_V7_HAS_NONSEC
672 select CPU_V7_HAS_VIRT
676 bool "Broadcom BCM7XXX family"
680 select OF_PRIOR_STAGE
683 This enables support for Broadcom ARM-based set-top box
684 chipsets, including the 7445 family of chips.
686 config TARGET_VEXPRESS_CA5X2
687 bool "Support vexpress_ca5x2"
691 config TARGET_VEXPRESS_CA9X4
692 bool "Support vexpress_ca9x4"
696 config TARGET_BCM23550_W1D
697 bool "Support bcm23550_w1d"
702 config TARGET_BCM28155_AP
703 bool "Support bcm28155_ap"
708 config TARGET_BCMCYGNUS
709 bool "Support bcmcygnus"
712 imply BCM_SF2_ETH_GMAC
720 bool "Support bcmnsp"
724 bool "Support Broadcom Northstar2"
727 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
728 ARMv8 Cortex-A57 processors targeting a broad range of networking
732 bool "Samsung EXYNOS"
741 imply SYS_THUMB_BUILD
746 bool "Samsung S5PC1XX"
755 bool "Calxeda Highbank"
759 config ARCH_INTEGRATOR
760 bool "ARM Ltd. Integrator family"
771 select SYS_ARCH_TIMER
772 select SYS_THUMB_BUILD
778 bool "Texas Instruments' K3 Architecture"
783 config ARCH_OMAP2PLUS
786 select SPL_BOARD_INIT if SPL
787 select SPL_STACK_R if SPL
793 imply DISTRO_DEFAULTS
796 Support for the Meson SoC family developed by Amlogic Inc.,
797 targeted at media players and tablet computers. We currently
798 support the S905 (GXBaby) 64-bit SoC.
805 select SPL_LIBCOMMON_SUPPORT if SPL
806 select SPL_LIBGENERIC_SUPPORT if SPL
807 select SPL_OF_CONTROL if SPL
810 Support for the MediaTek SoCs family developed by MediaTek Inc.
811 Please refer to doc/README.mediatek for more information.
814 bool "NXP LPC32xx platform"
824 bool "NXP i.MX8 platform"
828 select ENABLE_ARM_SOC_BOOT0_HOOK
831 bool "NXP i.MX8M platform"
838 bool "NXP i.MXRT platform"
846 bool "NXP i.MX23 family"
857 bool "NXP i.MX28 family"
863 bool "NXP i.MX31 family"
869 select ROM_UNIFIED_SECTIONS
871 imply SYS_THUMB_BUILD
875 select ARCH_MISC_INIT
876 select BOARD_EARLY_INIT_F
878 select SYS_FSL_HAS_SEC if IMX_HAB
879 select SYS_FSL_SEC_COMPAT_4
880 select SYS_FSL_SEC_LE
882 imply SYS_THUMB_BUILD
887 select SYS_FSL_HAS_SEC if IMX_HAB
888 select SYS_FSL_SEC_COMPAT_4
889 select SYS_FSL_SEC_LE
891 imply SYS_THUMB_BUILD
895 default "arch/arm/mach-omap2/u-boot-spl.lds"
900 select BOARD_EARLY_INIT_F
905 bool "Actions Semi OWL SoCs"
912 select SYS_RELOC_GD_ENV_ADDR
916 bool "QEMU Virtual Platform"
917 select ARCH_SUPPORT_TFABOOT
927 bool "Renesas ARM SoCs"
928 select BOARD_EARLY_INIT_F if !RZA1
933 imply SYS_THUMB_BUILD
934 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
936 config TARGET_S32V234EVB
937 bool "Support s32v234evb"
939 select SYS_FSL_ERRATUM_ESDHC111
941 config ARCH_SNAPDRAGON
942 bool "Qualcomm Snapdragon SoCs"
955 bool "Altera SOCFPGA family"
956 select ARCH_EARLY_INIT_R
957 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
958 select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
959 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
962 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
964 select SPL_DM_RESET if DM_RESET
966 select SPL_LIBCOMMON_SUPPORT
967 select SPL_LIBGENERIC_SUPPORT
968 select SPL_NAND_SUPPORT if SPL_NAND_DENALI
969 select SPL_OF_CONTROL
970 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
971 select SPL_SERIAL_SUPPORT
973 select SPL_WATCHDOG_SUPPORT
976 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
978 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
979 select SYSRESET_SOCFPGA_S10 if TARGET_SOCFPGA_STRATIX10
988 imply SPL_LIBDISK_SUPPORT
989 imply SPL_MMC_SUPPORT
990 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
991 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
992 imply SPL_SPI_FLASH_SUPPORT
993 imply SPL_SPI_SUPPORT
997 bool "Support sunxi (Allwinner) SoCs"
1000 select CMD_MMC if MMC
1001 select CMD_USB if DISTRO_DEFAULTS
1007 select DM_MMC if MMC
1008 select DM_SCSI if SCSI
1010 select DM_USB if DISTRO_DEFAULTS
1011 select OF_BOARD_SETUP
1014 select SPECIFY_CONSOLE_INDEX
1015 select SPL_STACK_R if SPL
1016 select SPL_SYS_MALLOC_SIMPLE if SPL
1017 select SPL_SYS_THUMB_BUILD if !ARM64
1020 select SYS_THUMB_BUILD if !ARM64
1021 select USB if DISTRO_DEFAULTS
1022 select USB_KEYBOARD if DISTRO_DEFAULTS
1023 select USB_STORAGE if DISTRO_DEFAULTS
1024 select SPL_USE_TINY_PRINTF
1026 select SYS_RELOC_GD_ENV_ADDR
1029 imply CMD_UBI if MTD_RAW_NAND
1030 imply DISTRO_DEFAULTS
1033 imply OF_LIBFDT_OVERLAY
1034 imply PRE_CONSOLE_BUFFER
1035 imply SPL_GPIO_SUPPORT
1036 imply SPL_LIBCOMMON_SUPPORT
1037 imply SPL_LIBGENERIC_SUPPORT
1038 imply SPL_MMC_SUPPORT if MMC
1039 imply SPL_POWER_SUPPORT
1040 imply SPL_SERIAL_SUPPORT
1044 bool "ST-Ericsson U8500 Series"
1048 select DM_MMC if MMC
1050 select DM_USB if USB
1054 imply ARM_PL180_MMCI
1056 imply NOMADIK_MTU_TIMER
1059 imply SYSRESET_SYSCON
1062 bool "Support Xilinx Versal Platform"
1066 select DM_ETH if NET
1067 select DM_MMC if MMC
1070 imply BOARD_LATE_INIT
1073 bool "Freescale Vybrid"
1075 select SYS_FSL_ERRATUM_ESDHC111
1080 bool "Xilinx Zynq based platform"
1085 select DM_ETH if NET
1086 select DM_MMC if MMC
1090 select DM_USB if USB
1093 select SPL_BOARD_INIT if SPL
1094 select SPL_CLK if SPL
1095 select SPL_DM if SPL
1096 select SPL_OF_CONTROL if SPL
1097 select SPL_SEPARATE_BSS if SPL
1099 imply ARCH_EARLY_INIT_R
1100 imply BOARD_LATE_INIT
1106 config ARCH_ZYNQMP_R5
1107 bool "Xilinx ZynqMP R5 based platform"
1111 select DM_ETH if NET
1112 select DM_MMC if MMC
1119 bool "Xilinx ZynqMP based platform"
1123 select DM_ETH if NET
1125 select DM_MMC if MMC
1127 select DM_SPI if SPI
1128 select DM_SPI_FLASH if DM_SPI
1129 select DM_USB if USB
1132 select SPL_BOARD_INIT if SPL
1133 select SPL_CLK if SPL
1134 select SPL_DM_MAILBOX if SPL
1135 select SPL_FIRMWARE if SPL
1136 select SPL_SEPARATE_BSS if SPL
1139 imply BOARD_LATE_INIT
1147 imply DISTRO_DEFAULTS
1150 config TARGET_VEXPRESS64_AEMV8A
1151 bool "Support vexpress_aemv8a"
1155 config TARGET_VEXPRESS64_BASE_FVP
1156 bool "Support Versatile Express ARMv8a FVP BASE model"
1161 config TARGET_VEXPRESS64_JUNO
1162 bool "Support Versatile Express Juno Development Platform"
1166 config TARGET_LS2080A_EMU
1167 bool "Support ls2080a_emu"
1170 select ARMV8_MULTIENTRY
1171 select FSL_DDR_SYNC_REFRESH
1173 Support for Freescale LS2080A_EMU platform.
1174 The LS2080A Development System (EMULATOR) is a pre-silicon
1175 development platform that supports the QorIQ LS2080A
1176 Layerscape Architecture processor.
1178 config TARGET_LS2080A_SIMU
1179 bool "Support ls2080a_simu"
1182 select ARMV8_MULTIENTRY
1183 select BOARD_LATE_INIT
1185 Support for Freescale LS2080A_SIMU platform.
1186 The LS2080A Development System (QDS) is a pre silicon
1187 development platform that supports the QorIQ LS2080A
1188 Layerscape Architecture processor.
1190 config TARGET_LS1088AQDS
1191 bool "Support ls1088aqds"
1194 select ARMV8_MULTIENTRY
1195 select ARCH_SUPPORT_TFABOOT
1196 select BOARD_LATE_INIT
1198 select FSL_DDR_INTERACTIVE if !SD_BOOT
1200 Support for NXP LS1088AQDS platform.
1201 The LS1088A Development System (QDS) is a high-performance
1202 development platform that supports the QorIQ LS1088A
1203 Layerscape Architecture processor.
1205 config TARGET_LS2080AQDS
1206 bool "Support ls2080aqds"
1209 select ARMV8_MULTIENTRY
1210 select ARCH_SUPPORT_TFABOOT
1211 select BOARD_LATE_INIT
1216 select FSL_DDR_INTERACTIVE if !SPL
1218 Support for Freescale LS2080AQDS platform.
1219 The LS2080A Development System (QDS) is a high-performance
1220 development platform that supports the QorIQ LS2080A
1221 Layerscape Architecture processor.
1223 config TARGET_LS2080ARDB
1224 bool "Support ls2080ardb"
1227 select ARMV8_MULTIENTRY
1228 select ARCH_SUPPORT_TFABOOT
1229 select BOARD_LATE_INIT
1232 select FSL_DDR_INTERACTIVE if !SPL
1236 Support for Freescale LS2080ARDB platform.
1237 The LS2080A Reference design board (RDB) is a high-performance
1238 development platform that supports the QorIQ LS2080A
1239 Layerscape Architecture processor.
1241 config TARGET_LS2081ARDB
1242 bool "Support ls2081ardb"
1245 select ARMV8_MULTIENTRY
1246 select BOARD_LATE_INIT
1249 Support for Freescale LS2081ARDB platform.
1250 The LS2081A Reference design board (RDB) is a high-performance
1251 development platform that supports the QorIQ LS2081A/LS2041A
1252 Layerscape Architecture processor.
1254 config TARGET_LX2160ARDB
1255 bool "Support lx2160ardb"
1258 select ARMV8_MULTIENTRY
1259 select ARCH_SUPPORT_TFABOOT
1260 select BOARD_LATE_INIT
1262 Support for NXP LX2160ARDB platform.
1263 The lx2160ardb (LX2160A Reference design board (RDB)
1264 is a high-performance development platform that supports the
1265 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1267 config TARGET_LX2160AQDS
1268 bool "Support lx2160aqds"
1271 select ARMV8_MULTIENTRY
1272 select ARCH_SUPPORT_TFABOOT
1273 select BOARD_LATE_INIT
1275 Support for NXP LX2160AQDS platform.
1276 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1277 is a high-performance development platform that supports the
1278 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1281 bool "Support HiKey 96boards Consumer Edition Platform"
1288 select SPECIFY_CONSOLE_INDEX
1291 Support for HiKey 96boards platform. It features a HI6220
1292 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1294 config TARGET_HIKEY960
1295 bool "Support HiKey960 96boards Consumer Edition Platform"
1303 Support for HiKey960 96boards platform. It features a HI3660
1304 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1306 config TARGET_POPLAR
1307 bool "Support Poplar 96boards Enterprise Edition Platform"
1316 Support for Poplar 96boards EE platform. It features a HI3798cv200
1317 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1318 making it capable of running any commercial set-top solution based on
1321 config TARGET_LS1012AQDS
1322 bool "Support ls1012aqds"
1325 select ARCH_SUPPORT_TFABOOT
1326 select BOARD_LATE_INIT
1328 Support for Freescale LS1012AQDS platform.
1329 The LS1012A Development System (QDS) is a high-performance
1330 development platform that supports the QorIQ LS1012A
1331 Layerscape Architecture processor.
1333 config TARGET_LS1012ARDB
1334 bool "Support ls1012ardb"
1337 select ARCH_SUPPORT_TFABOOT
1338 select BOARD_LATE_INIT
1342 Support for Freescale LS1012ARDB platform.
1343 The LS1012A Reference design board (RDB) is a high-performance
1344 development platform that supports the QorIQ LS1012A
1345 Layerscape Architecture processor.
1347 config TARGET_LS1012A2G5RDB
1348 bool "Support ls1012a2g5rdb"
1351 select ARCH_SUPPORT_TFABOOT
1352 select BOARD_LATE_INIT
1355 Support for Freescale LS1012A2G5RDB platform.
1356 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1357 development platform that supports the QorIQ LS1012A
1358 Layerscape Architecture processor.
1360 config TARGET_LS1012AFRWY
1361 bool "Support ls1012afrwy"
1364 select ARCH_SUPPORT_TFABOOT
1365 select BOARD_LATE_INIT
1369 Support for Freescale LS1012AFRWY platform.
1370 The LS1012A FRWY board (FRWY) is a high-performance
1371 development platform that supports the QorIQ LS1012A
1372 Layerscape Architecture processor.
1374 config TARGET_LS1012AFRDM
1375 bool "Support ls1012afrdm"
1378 select ARCH_SUPPORT_TFABOOT
1380 Support for Freescale LS1012AFRDM platform.
1381 The LS1012A Freedom board (FRDM) is a high-performance
1382 development platform that supports the QorIQ LS1012A
1383 Layerscape Architecture processor.
1385 config TARGET_LS1028AQDS
1386 bool "Support ls1028aqds"
1389 select ARMV8_MULTIENTRY
1390 select ARCH_SUPPORT_TFABOOT
1391 select BOARD_LATE_INIT
1393 Support for Freescale LS1028AQDS platform
1394 The LS1028A Development System (QDS) is a high-performance
1395 development platform that supports the QorIQ LS1028A
1396 Layerscape Architecture processor.
1398 config TARGET_LS1028ARDB
1399 bool "Support ls1028ardb"
1402 select ARMV8_MULTIENTRY
1403 select ARCH_SUPPORT_TFABOOT
1404 select BOARD_LATE_INIT
1406 Support for Freescale LS1028ARDB platform
1407 The LS1028A Development System (RDB) is a high-performance
1408 development platform that supports the QorIQ LS1028A
1409 Layerscape Architecture processor.
1411 config TARGET_LS1088ARDB
1412 bool "Support ls1088ardb"
1415 select ARMV8_MULTIENTRY
1416 select ARCH_SUPPORT_TFABOOT
1417 select BOARD_LATE_INIT
1419 select FSL_DDR_INTERACTIVE if !SD_BOOT
1421 Support for NXP LS1088ARDB platform.
1422 The LS1088A Reference design board (RDB) is a high-performance
1423 development platform that supports the QorIQ LS1088A
1424 Layerscape Architecture processor.
1426 config TARGET_LS1021AQDS
1427 bool "Support ls1021aqds"
1429 select ARCH_SUPPORT_PSCI
1430 select BOARD_EARLY_INIT_F
1431 select BOARD_LATE_INIT
1433 select CPU_V7_HAS_NONSEC
1434 select CPU_V7_HAS_VIRT
1435 select LS1_DEEP_SLEEP
1438 select FSL_DDR_INTERACTIVE
1441 config TARGET_LS1021ATWR
1442 bool "Support ls1021atwr"
1444 select ARCH_SUPPORT_PSCI
1445 select BOARD_EARLY_INIT_F
1446 select BOARD_LATE_INIT
1448 select CPU_V7_HAS_NONSEC
1449 select CPU_V7_HAS_VIRT
1450 select LS1_DEEP_SLEEP
1454 config TARGET_LS1021ATSN
1455 bool "Support ls1021atsn"
1457 select ARCH_SUPPORT_PSCI
1458 select BOARD_EARLY_INIT_F
1459 select BOARD_LATE_INIT
1461 select CPU_V7_HAS_NONSEC
1462 select CPU_V7_HAS_VIRT
1463 select LS1_DEEP_SLEEP
1467 config TARGET_LS1021AIOT
1468 bool "Support ls1021aiot"
1470 select ARCH_SUPPORT_PSCI
1471 select BOARD_LATE_INIT
1473 select CPU_V7_HAS_NONSEC
1474 select CPU_V7_HAS_VIRT
1478 Support for Freescale LS1021AIOT platform.
1479 The LS1021A Freescale board (IOT) is a high-performance
1480 development platform that supports the QorIQ LS1021A
1481 Layerscape Architecture processor.
1483 config TARGET_LS1043AQDS
1484 bool "Support ls1043aqds"
1487 select ARMV8_MULTIENTRY
1488 select ARCH_SUPPORT_TFABOOT
1489 select BOARD_EARLY_INIT_F
1490 select BOARD_LATE_INIT
1492 select FSL_DDR_INTERACTIVE if !SPL
1496 Support for Freescale LS1043AQDS platform.
1498 config TARGET_LS1043ARDB
1499 bool "Support ls1043ardb"
1502 select ARMV8_MULTIENTRY
1503 select ARCH_SUPPORT_TFABOOT
1504 select BOARD_EARLY_INIT_F
1505 select BOARD_LATE_INIT
1508 Support for Freescale LS1043ARDB platform.
1510 config TARGET_LS1046AQDS
1511 bool "Support ls1046aqds"
1514 select ARMV8_MULTIENTRY
1515 select ARCH_SUPPORT_TFABOOT
1516 select BOARD_EARLY_INIT_F
1517 select BOARD_LATE_INIT
1518 select DM_SPI_FLASH if DM_SPI
1520 select FSL_DDR_BIST if !SPL
1521 select FSL_DDR_INTERACTIVE if !SPL
1522 select FSL_DDR_INTERACTIVE if !SPL
1525 Support for Freescale LS1046AQDS platform.
1526 The LS1046A Development System (QDS) is a high-performance
1527 development platform that supports the QorIQ LS1046A
1528 Layerscape Architecture processor.
1530 config TARGET_LS1046ARDB
1531 bool "Support ls1046ardb"
1534 select ARMV8_MULTIENTRY
1535 select ARCH_SUPPORT_TFABOOT
1536 select BOARD_EARLY_INIT_F
1537 select BOARD_LATE_INIT
1538 select DM_SPI_FLASH if DM_SPI
1539 select POWER_MC34VR500
1542 select FSL_DDR_INTERACTIVE if !SPL
1545 Support for Freescale LS1046ARDB platform.
1546 The LS1046A Reference Design Board (RDB) is a high-performance
1547 development platform that supports the QorIQ LS1046A
1548 Layerscape Architecture processor.
1550 config TARGET_LS1046AFRWY
1551 bool "Support ls1046afrwy"
1554 select ARMV8_MULTIENTRY
1555 select ARCH_SUPPORT_TFABOOT
1556 select BOARD_EARLY_INIT_F
1557 select BOARD_LATE_INIT
1558 select DM_SPI_FLASH if DM_SPI
1561 Support for Freescale LS1046AFRWY platform.
1562 The LS1046A Freeway Board (FRWY) is a high-performance
1563 development platform that supports the QorIQ LS1046A
1564 Layerscape Architecture processor.
1566 config TARGET_COLIBRI_PXA270
1567 bool "Support colibri_pxa270"
1570 config ARCH_UNIPHIER
1571 bool "Socionext UniPhier SoCs"
1572 select BOARD_LATE_INIT
1581 select OF_BOARD_SETUP
1585 select SPL_BOARD_INIT if SPL
1586 select SPL_DM if SPL
1587 select SPL_LIBCOMMON_SUPPORT if SPL
1588 select SPL_LIBGENERIC_SUPPORT if SPL
1589 select SPL_OF_CONTROL if SPL
1590 select SPL_PINCTRL if SPL
1593 imply DISTRO_DEFAULTS
1596 Support for UniPhier SoC family developed by Socionext Inc.
1597 (formerly, System LSI Business Division of Panasonic Corporation)
1600 bool "Support STMicroelectronics STM32 MCU with cortex M"
1607 bool "Support STMicrolectronics SoCs"
1616 Support for STMicroelectronics STiH407/10 SoC family.
1617 This SoC is used on Linaro 96Board STiH410-B2260
1620 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1621 select ARCH_MISC_INIT
1622 select ARCH_SUPPORT_TFABOOT
1623 select BOARD_LATE_INIT
1632 select OF_SYSTEM_SETUP
1638 select SYS_THUMB_BUILD
1642 imply OF_LIBFDT_OVERLAY
1643 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1646 Support for STM32MP SoC family developed by STMicroelectronics,
1647 MPUs based on ARM cortex A core
1648 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1649 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
1651 SPL is the unsecure FSBL for the basic boot chain.
1653 config ARCH_ROCKCHIP
1654 bool "Support Rockchip SoCs"
1656 select BINMAN if !ARM64
1666 select DM_USB if USB
1667 select ENABLE_ARM_SOC_BOOT0_HOOK
1670 select SPL_DM if SPL
1672 select SYS_THUMB_BUILD if !ARM64
1675 imply DEBUG_UART_BOARD_INIT
1676 imply DISTRO_DEFAULTS
1678 imply SARADC_ROCKCHIP
1680 imply SPL_SYS_MALLOC_SIMPLE
1683 imply USB_FUNCTION_FASTBOOT
1685 config TARGET_THUNDERX_88XX
1686 bool "Support ThunderX 88xx"
1690 select SYS_CACHE_SHIFT_7
1693 bool "Support Aspeed SoCs"
1698 config TARGET_DURIAN
1699 bool "Support Phytium Durian Platform"
1702 Support for durian platform.
1703 It has 2GB Sdram, uart and pcie.
1705 config TARGET_PRESIDIO_ASIC
1706 bool "Support Cortina Presidio ASIC Platform"
1711 config ARCH_SUPPORT_TFABOOT
1715 bool "Support for booting from TF-A"
1716 depends on ARCH_SUPPORT_TFABOOT
1719 Enabling this will make a U-Boot binary that is capable of being
1720 booted via TF-A (Trusted Firmware for Cortex-A).
1722 config TI_SECURE_DEVICE
1723 bool "HS Device Type Support"
1724 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
1726 If a high secure (HS) device type is being used, this config
1727 must be set. This option impacts various aspects of the
1728 build system (to create signed boot images that can be
1729 authenticated) and the code. See the doc/README.ti-secure
1730 file for further details.
1732 if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
1733 config ISW_ENTRY_ADDR
1734 hex "Address in memory or XIP address of bootloader entry point"
1735 default 0x402F4000 if AM43XX
1736 default 0x402F0400 if AM33XX
1737 default 0x40301350 if OMAP54XX
1739 After any reset, the boot ROM searches the boot media for a valid
1740 boot image. For non-XIP devices, the ROM then copies the image into
1741 internal memory. For all boot modes, after the ROM processes the
1742 boot image it eventually computes the entry point address depending
1743 on the device type (secure/non-secure), boot media (xip/non-xip) and
1747 source "arch/arm/mach-aspeed/Kconfig"
1749 source "arch/arm/mach-at91/Kconfig"
1751 source "arch/arm/mach-bcm283x/Kconfig"
1753 source "arch/arm/mach-bcmstb/Kconfig"
1755 source "arch/arm/mach-davinci/Kconfig"
1757 source "arch/arm/mach-exynos/Kconfig"
1759 source "arch/arm/mach-highbank/Kconfig"
1761 source "arch/arm/mach-integrator/Kconfig"
1763 source "arch/arm/mach-k3/Kconfig"
1765 source "arch/arm/mach-keystone/Kconfig"
1767 source "arch/arm/mach-kirkwood/Kconfig"
1769 source "arch/arm/cpu/arm926ejs/lpc32xx/Kconfig"
1771 source "arch/arm/mach-mvebu/Kconfig"
1773 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
1775 source "arch/arm/mach-imx/mx2/Kconfig"
1777 source "arch/arm/mach-imx/mx3/Kconfig"
1779 source "arch/arm/mach-imx/mx5/Kconfig"
1781 source "arch/arm/mach-imx/mx6/Kconfig"
1783 source "arch/arm/mach-imx/mx7/Kconfig"
1785 source "arch/arm/mach-imx/mx7ulp/Kconfig"
1787 source "arch/arm/mach-imx/imx8/Kconfig"
1789 source "arch/arm/mach-imx/imx8m/Kconfig"
1791 source "arch/arm/mach-imx/imxrt/Kconfig"
1793 source "arch/arm/mach-imx/mxs/Kconfig"
1795 source "arch/arm/mach-omap2/Kconfig"
1797 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
1799 source "arch/arm/mach-orion5x/Kconfig"
1801 source "arch/arm/mach-owl/Kconfig"
1803 source "arch/arm/mach-rmobile/Kconfig"
1805 source "arch/arm/mach-meson/Kconfig"
1807 source "arch/arm/mach-mediatek/Kconfig"
1809 source "arch/arm/mach-qemu/Kconfig"
1811 source "arch/arm/mach-rockchip/Kconfig"
1813 source "arch/arm/mach-s5pc1xx/Kconfig"
1815 source "arch/arm/mach-snapdragon/Kconfig"
1817 source "arch/arm/mach-socfpga/Kconfig"
1819 source "arch/arm/mach-sti/Kconfig"
1821 source "arch/arm/mach-stm32/Kconfig"
1823 source "arch/arm/mach-stm32mp/Kconfig"
1825 source "arch/arm/mach-sunxi/Kconfig"
1827 source "arch/arm/mach-tegra/Kconfig"
1829 source "arch/arm/mach-u8500/Kconfig"
1831 source "arch/arm/mach-uniphier/Kconfig"
1833 source "arch/arm/cpu/armv7/vf610/Kconfig"
1835 source "arch/arm/mach-zynq/Kconfig"
1837 source "arch/arm/mach-zynqmp/Kconfig"
1839 source "arch/arm/mach-versal/Kconfig"
1841 source "arch/arm/mach-zynqmp-r5/Kconfig"
1843 source "arch/arm/cpu/armv7/Kconfig"
1845 source "arch/arm/cpu/armv8/Kconfig"
1847 source "arch/arm/mach-imx/Kconfig"
1849 source "board/bosch/shc/Kconfig"
1850 source "board/bosch/guardian/Kconfig"
1851 source "board/CarMediaLab/flea3/Kconfig"
1852 source "board/Marvell/aspenite/Kconfig"
1853 source "board/Marvell/gplugd/Kconfig"
1854 source "board/armadeus/apf27/Kconfig"
1855 source "board/armltd/vexpress/Kconfig"
1856 source "board/armltd/vexpress64/Kconfig"
1857 source "board/cortina/presidio-asic/Kconfig"
1858 source "board/broadcom/bcm23550_w1d/Kconfig"
1859 source "board/broadcom/bcm28155_ap/Kconfig"
1860 source "board/broadcom/bcm963158/Kconfig"
1861 source "board/broadcom/bcm968360bg/Kconfig"
1862 source "board/broadcom/bcm968580xref/Kconfig"
1863 source "board/broadcom/bcmcygnus/Kconfig"
1864 source "board/broadcom/bcmnsp/Kconfig"
1865 source "board/broadcom/bcmns2/Kconfig"
1866 source "board/cavium/thunderx/Kconfig"
1867 source "board/cirrus/edb93xx/Kconfig"
1868 source "board/eets/pdu001/Kconfig"
1869 source "board/emulation/qemu-arm/Kconfig"
1870 source "board/freescale/ls2080a/Kconfig"
1871 source "board/freescale/ls2080aqds/Kconfig"
1872 source "board/freescale/ls2080ardb/Kconfig"
1873 source "board/freescale/ls1088a/Kconfig"
1874 source "board/freescale/ls1028a/Kconfig"
1875 source "board/freescale/ls1021aqds/Kconfig"
1876 source "board/freescale/ls1043aqds/Kconfig"
1877 source "board/freescale/ls1021atwr/Kconfig"
1878 source "board/freescale/ls1021atsn/Kconfig"
1879 source "board/freescale/ls1021aiot/Kconfig"
1880 source "board/freescale/ls1046aqds/Kconfig"
1881 source "board/freescale/ls1043ardb/Kconfig"
1882 source "board/freescale/ls1046ardb/Kconfig"
1883 source "board/freescale/ls1046afrwy/Kconfig"
1884 source "board/freescale/ls1012aqds/Kconfig"
1885 source "board/freescale/ls1012ardb/Kconfig"
1886 source "board/freescale/ls1012afrdm/Kconfig"
1887 source "board/freescale/lx2160a/Kconfig"
1888 source "board/freescale/mx35pdk/Kconfig"
1889 source "board/freescale/s32v234evb/Kconfig"
1890 source "board/grinn/chiliboard/Kconfig"
1891 source "board/gumstix/pepper/Kconfig"
1892 source "board/hisilicon/hikey/Kconfig"
1893 source "board/hisilicon/hikey960/Kconfig"
1894 source "board/hisilicon/poplar/Kconfig"
1895 source "board/isee/igep003x/Kconfig"
1896 source "board/phytec/pcm051/Kconfig"
1897 source "board/silica/pengwyn/Kconfig"
1898 source "board/spear/spear300/Kconfig"
1899 source "board/spear/spear310/Kconfig"
1900 source "board/spear/spear320/Kconfig"
1901 source "board/spear/spear600/Kconfig"
1902 source "board/spear/x600/Kconfig"
1903 source "board/st/stv0991/Kconfig"
1904 source "board/tcl/sl50/Kconfig"
1905 source "board/birdland/bav335x/Kconfig"
1906 source "board/toradex/colibri_pxa270/Kconfig"
1907 source "board/variscite/dart_6ul/Kconfig"
1908 source "board/vscom/baltos/Kconfig"
1909 source "board/xilinx/Kconfig"
1910 source "board/xilinx/zynq/Kconfig"
1911 source "board/xilinx/zynqmp/Kconfig"
1912 source "board/phytium/durian/Kconfig"
1914 source "arch/arm/Kconfig.debug"
1919 default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
1920 default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
1921 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64