1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
8 #include <linux/compiler.h>
9 #include <linux/kernel.h>
10 #include <linux/log2.h>
11 #include <asm/arcregs.h>
12 #include <asm/arc-bcr.h>
13 #include <asm/cache.h>
17 * Data cache (L1 D$ or SL$) entire invalidate operation or data cache disable
18 * operation may result in unexpected behavior and data loss even if we flush
19 * data cache right before invalidation. That may happens if we store any context
20 * on stack (like we store BLINK register on stack before function call).
21 * BLINK register is the register where return address is automatically saved
22 * when we do function call with instructions like 'bl'.
24 * There is the real example:
25 * We may hang in the next code as we store any BLINK register on stack in
26 * invalidate_dcache_all() function.
28 * void flush_dcache_all() {
29 * __dc_entire_op(OP_FLUSH);
33 * void invalidate_dcache_all() {
34 * __dc_entire_op(OP_INV);
40 * invalidate_dcache_all();
43 * Now let's see what really happens during that code execution:
46 * |->> call flush_dcache_all
47 * [return address is saved to BLINK register]
48 * [push BLINK] (save to stack) ![point 1]
49 * |->> call __dc_entire_op(OP_FLUSH)
50 * [return address is saved to BLINK register]
52 * return [jump to BLINK]
54 * [other flush_dcache_all code]
55 * [pop BLINK] (get from stack)
56 * return [jump to BLINK]
58 * |->> call invalidate_dcache_all
59 * [return address is saved to BLINK register]
60 * [push BLINK] (save to stack) ![point 2]
61 * |->> call __dc_entire_op(OP_FLUSH)
62 * [return address is saved to BLINK register]
63 * [invalidate L1 D$] ![point 3]
65 * // We lose return address from invalidate_dcache_all function:
66 * // we save it to stack and invalidate L1 D$ after that!
67 * return [jump to BLINK]
69 * [other invalidate_dcache_all code]
70 * [pop BLINK] (get from stack)
71 * // we don't have this data in L1 dcache as we invalidated it in [point 3]
72 * // so we get it from next memory level (for example DDR memory)
73 * // but in the memory we have value which we save in [point 1], which
74 * // is return address from flush_dcache_all function (instead of
75 * // address from current invalidate_dcache_all function which we
76 * // saved in [point 2] !)
77 * return [jump to BLINK]
79 * // As BLINK points to invalidate_dcache_all, we call it again and
82 * Fortunately we may fix that by using flush & invalidation of D$ with a single
83 * one instruction (instead of flush and invalidation instructions pair) and
84 * enabling force function inline with '__attribute__((always_inline))' gcc
85 * attribute to avoid any function call (and BLINK store) between cache flush
90 * As of today we only support the following cache configurations on ARC.
91 * Other configurations may exist in HW (for example, since version 3.0 HS
92 * supports SL$ (L2 system level cache) disable) but we don't support it in SW.
94 * ______________________
97 * |______________________|
100 * | L1 I$ | | L1 D$ |
101 * |_______| |_______|
103 * ___|______________|____
106 * |______________________|
109 * ______________________
112 * |______________________|
115 * | L1 I$ | | L1 D$ |
116 * |_______| |_______|
118 * ___|______________|____
121 * |______________________|
123 * ___|______________|____
126 * |______________________|
129 * ______________________
132 * |______________________|
135 * | L1 I$ | | L1 D$ |
136 * |_______| |_______|
138 * ___|______________|____ _______
140 * | L2 (SL$) |-----| IOC |
141 * |______________________| |_______|
142 * always must be on on/off
143 * ___|______________|____
146 * |______________________|
149 DECLARE_GLOBAL_DATA_PTR;
151 /* Bit values in IC_CTRL */
152 #define IC_CTRL_CACHE_DISABLE BIT(0)
154 /* Bit values in DC_CTRL */
155 #define DC_CTRL_CACHE_DISABLE BIT(0)
156 #define DC_CTRL_INV_MODE_FLUSH BIT(6)
157 #define DC_CTRL_FLUSH_STATUS BIT(8)
159 #define OP_INV BIT(0)
160 #define OP_FLUSH BIT(1)
161 #define OP_FLUSH_N_INV (OP_FLUSH | OP_INV)
163 /* Bit val in SLC_CONTROL */
164 #define SLC_CTRL_DIS 0x001
165 #define SLC_CTRL_IM 0x040
166 #define SLC_CTRL_BUSY 0x100
167 #define SLC_CTRL_RGN_OP_INV 0x200
169 #define CACHE_LINE_MASK (~(gd->arch.l1_line_sz - 1))
172 * We don't want to use '__always_inline' macro here as it can be redefined
173 * to simple 'inline' in some cases which breaks stuff. See [ NOTE 1 ] for more
174 * details about the reasons we need to use always_inline functions.
176 #define inlined_cachefunc inline __attribute__((always_inline))
178 static inlined_cachefunc void __ic_entire_invalidate(void);
179 static inlined_cachefunc void __dc_entire_op(const int cacheop);
181 static inline bool pae_exists(void)
183 /* TODO: should we compare mmu version from BCR and from CONFIG? */
184 #if (CONFIG_ARC_MMU_VER >= 4)
185 union bcr_mmu_4 mmu4;
187 mmu4.word = read_aux_reg(ARC_AUX_MMU_BCR);
191 #endif /* (CONFIG_ARC_MMU_VER >= 4) */
196 static inlined_cachefunc bool icache_exists(void)
198 union bcr_di_cache ibcr;
200 ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
201 return !!ibcr.fields.ver;
204 static inlined_cachefunc bool icache_enabled(void)
206 if (!icache_exists())
209 return !(read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE);
212 static inlined_cachefunc bool dcache_exists(void)
214 union bcr_di_cache dbcr;
216 dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
217 return !!dbcr.fields.ver;
220 static inlined_cachefunc bool dcache_enabled(void)
222 if (!dcache_exists())
225 return !(read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE);
228 static inlined_cachefunc bool slc_exists(void)
230 if (is_isa_arcv2()) {
231 union bcr_generic sbcr;
233 sbcr.word = read_aux_reg(ARC_BCR_SLC);
234 return !!sbcr.fields.ver;
240 static inlined_cachefunc bool slc_data_bypass(void)
243 * If L1 data cache is disabled SL$ is bypassed and all load/store
244 * requests are sent directly to main memory.
246 return !dcache_enabled();
249 static inline bool ioc_exists(void)
251 if (is_isa_arcv2()) {
252 union bcr_clust_cfg cbcr;
254 cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
255 return cbcr.fields.c;
261 static inline bool ioc_enabled(void)
264 * We check only CONFIG option instead of IOC HW state check as IOC
265 * must be disabled by default.
267 if (is_ioc_enabled())
273 static inlined_cachefunc void __slc_entire_op(const int op)
280 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
282 if (!(op & OP_FLUSH)) /* i.e. OP_INV */
283 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
287 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
289 if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */
290 write_aux_reg(ARC_AUX_SLC_INVALIDATE, 0x1);
292 write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1);
294 /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
295 read_aux_reg(ARC_AUX_SLC_CTRL);
297 /* Important to wait for flush to complete */
298 while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY);
301 static void slc_upper_region_init(void)
304 * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist
305 * only if PAE exists in current HW. So we had to check pae_exist
312 * ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1 are always == 0
313 * as we don't use PAE40.
315 write_aux_reg(ARC_AUX_SLC_RGN_END1, 0);
316 write_aux_reg(ARC_AUX_SLC_RGN_START1, 0);
319 static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op)
321 #ifdef CONFIG_ISA_ARCV2
330 * The Region Flush operation is specified by CTRL.RGN_OP[11..9]
331 * - b'000 (default) is Flush,
332 * - b'001 is Invalidate if CTRL.IM == 0
333 * - b'001 is Flush-n-Invalidate if CTRL.IM == 1
335 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
337 /* Don't rely on default value of IM bit */
338 if (!(op & OP_FLUSH)) /* i.e. OP_INV */
339 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
344 ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */
346 ctrl &= ~SLC_CTRL_RGN_OP_INV;
348 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
351 * Lower bits are ignored, no need to clip
352 * END needs to be setup before START (latter triggers the operation)
353 * END can't be same as START, so add (l2_line_sz - 1) to sz
355 end = paddr + sz + gd->arch.slc_line_sz - 1;
358 * Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1)
359 * are always == 0 as we don't use PAE40, so we only setup lower ones
360 * (ARC_AUX_SLC_RGN_END and ARC_AUX_SLC_RGN_START)
362 write_aux_reg(ARC_AUX_SLC_RGN_END, end);
363 write_aux_reg(ARC_AUX_SLC_RGN_START, paddr);
365 /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
366 read_aux_reg(ARC_AUX_SLC_CTRL);
368 while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY);
370 #endif /* CONFIG_ISA_ARCV2 */
373 static void arc_ioc_setup(void)
375 /* IOC Aperture start is equal to DDR start */
376 unsigned int ap_base = CONFIG_SYS_SDRAM_BASE;
377 /* IOC Aperture size is equal to DDR size */
378 long ap_size = CONFIG_SYS_SDRAM_SIZE;
380 /* Unsupported configuration. See [ NOTE 2 ] for more details. */
382 panic("Try to enable IOC but SLC is not present");
384 /* Unsupported configuration. See [ NOTE 2 ] for more details. */
385 if (!dcache_enabled())
386 panic("Try to enable IOC but L1 D$ is disabled");
388 if (!is_power_of_2(ap_size) || ap_size < 4096)
389 panic("IOC Aperture size must be power of 2 and bigger 4Kib");
391 /* IOC Aperture start must be aligned to the size of the aperture */
392 if (ap_base % ap_size != 0)
393 panic("IOC Aperture start must be aligned to the size of the aperture");
395 flush_n_invalidate_dcache_all();
398 * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB,
399 * so setting 0x11 implies 512M, 0x12 implies 1G...
401 write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE,
402 order_base_2(ap_size / 1024) - 2);
404 write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12);
405 write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1);
406 write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1);
409 static void read_decode_cache_bcr_arcv2(void)
411 #ifdef CONFIG_ISA_ARCV2
413 union bcr_slc_cfg slc_cfg;
416 slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG);
417 gd->arch.slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64;
420 * We don't support configuration where L1 I$ or L1 D$ is
421 * absent but SL$ exists. See [ NOTE 2 ] for more details.
423 if (!icache_exists() || !dcache_exists())
424 panic("Unsupported cache configuration: SLC exists but one of L1 caches is absent");
427 #endif /* CONFIG_ISA_ARCV2 */
430 void read_decode_cache_bcr(void)
432 int dc_line_sz = 0, ic_line_sz = 0;
433 union bcr_di_cache ibcr, dbcr;
436 * We don't care much about I$ line length really as there're
437 * no per-line ops on I$ instead we only do full invalidation of it
438 * on occasion of relocation and right before jumping to the OS.
439 * Still we check insane config with zero-encoded line length in
440 * presense of version field in I$ BCR. Just in case.
442 ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
443 if (ibcr.fields.ver) {
444 ic_line_sz = 8 << ibcr.fields.line_len;
446 panic("Instruction exists but line length is 0\n");
449 dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
450 if (dbcr.fields.ver) {
451 gd->arch.l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len;
453 panic("Data cache exists but line length is 0\n");
457 void cache_init(void)
459 read_decode_cache_bcr();
462 read_decode_cache_bcr_arcv2();
464 if (is_isa_arcv2() && ioc_enabled())
467 if (is_isa_arcv2() && slc_exists())
468 slc_upper_region_init();
471 int icache_status(void)
473 return icache_enabled();
476 void icache_enable(void)
479 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
480 ~IC_CTRL_CACHE_DISABLE);
483 void icache_disable(void)
485 if (!icache_exists())
488 __ic_entire_invalidate();
490 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
491 IC_CTRL_CACHE_DISABLE);
494 /* IC supports only invalidation */
495 static inlined_cachefunc void __ic_entire_invalidate(void)
497 if (!icache_enabled())
500 /* Any write to IC_IVIC register triggers invalidation of entire I$ */
501 write_aux_reg(ARC_AUX_IC_IVIC, 1);
503 * As per ARC HS databook (see chapter 5.3.3.2)
504 * it is required to add 3 NOPs after each write to IC_IVIC.
509 read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */
512 void invalidate_icache_all(void)
514 __ic_entire_invalidate();
517 * If SL$ is bypassed for data it is used only for instructions,
518 * so we need to invalidate it too.
519 * TODO: HS 3.0 supports SLC disable so we need to check slc
520 * enable/disable status here.
522 if (is_isa_arcv2() && slc_data_bypass())
523 __slc_entire_op(OP_INV);
526 int dcache_status(void)
528 return dcache_enabled();
531 void dcache_enable(void)
533 if (!dcache_exists())
536 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
537 ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
540 void dcache_disable(void)
542 if (!dcache_exists())
545 __dc_entire_op(OP_FLUSH_N_INV);
548 * As SLC will be bypassed for data after L1 D$ disable we need to
549 * flush it first before L1 D$ disable. Also we invalidate SLC to
550 * avoid any inconsistent data problems after enabling L1 D$ again with
551 * dcache_enable function.
554 __slc_entire_op(OP_FLUSH_N_INV);
556 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
557 DC_CTRL_CACHE_DISABLE);
560 /* Common Helper for Line Operations on D-cache */
561 static inline void __dcache_line_loop(unsigned long paddr, unsigned long sz,
564 unsigned int aux_cmd;
567 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
568 aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL;
570 sz += paddr & ~CACHE_LINE_MASK;
571 paddr &= CACHE_LINE_MASK;
573 num_lines = DIV_ROUND_UP(sz, gd->arch.l1_line_sz);
575 while (num_lines-- > 0) {
576 #if (CONFIG_ARC_MMU_VER == 3)
577 write_aux_reg(ARC_AUX_DC_PTAG, paddr);
579 write_aux_reg(aux_cmd, paddr);
580 paddr += gd->arch.l1_line_sz;
584 static inlined_cachefunc void __before_dc_op(const int op)
588 ctrl = read_aux_reg(ARC_AUX_DC_CTRL);
590 /* IM bit implies flush-n-inv, instead of vanilla inv */
592 ctrl &= ~DC_CTRL_INV_MODE_FLUSH;
594 ctrl |= DC_CTRL_INV_MODE_FLUSH;
596 write_aux_reg(ARC_AUX_DC_CTRL, ctrl);
599 static inlined_cachefunc void __after_dc_op(const int op)
601 if (op & OP_FLUSH) /* flush / flush-n-inv both wait */
602 while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
605 static inlined_cachefunc void __dc_entire_op(const int cacheop)
609 if (!dcache_enabled())
612 __before_dc_op(cacheop);
614 if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
615 aux = ARC_AUX_DC_IVDC;
617 aux = ARC_AUX_DC_FLSH;
619 write_aux_reg(aux, 0x1);
621 __after_dc_op(cacheop);
624 static inline void __dc_line_op(unsigned long paddr, unsigned long sz,
627 if (!dcache_enabled())
630 __before_dc_op(cacheop);
631 __dcache_line_loop(paddr, sz, cacheop);
632 __after_dc_op(cacheop);
635 void invalidate_dcache_range(unsigned long start, unsigned long end)
641 * ARCv1 -> call __dc_line_op
642 * ARCv2 && L1 D$ disabled -> nothing
643 * ARCv2 && L1 D$ enabled && IOC enabled -> nothing
644 * ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op
646 if (!is_isa_arcv2() || !ioc_enabled())
647 __dc_line_op(start, end - start, OP_INV);
649 if (is_isa_arcv2() && !ioc_enabled() && !slc_data_bypass())
650 __slc_rgn_op(start, end - start, OP_INV);
653 void flush_dcache_range(unsigned long start, unsigned long end)
659 * ARCv1 -> call __dc_line_op
660 * ARCv2 && L1 D$ disabled -> nothing
661 * ARCv2 && L1 D$ enabled && IOC enabled -> nothing
662 * ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op
664 if (!is_isa_arcv2() || !ioc_enabled())
665 __dc_line_op(start, end - start, OP_FLUSH);
667 if (is_isa_arcv2() && !ioc_enabled() && !slc_data_bypass())
668 __slc_rgn_op(start, end - start, OP_FLUSH);
671 void flush_cache(unsigned long start, unsigned long size)
673 flush_dcache_range(start, start + size);
677 * As invalidate_dcache_all() is not used in generic U-Boot code and as we
678 * don't need it in arch/arc code alone (invalidate without flush) we implement
679 * flush_n_invalidate_dcache_all (flush and invalidate in 1 operation) because
680 * it's much safer. See [ NOTE 1 ] for more details.
682 void flush_n_invalidate_dcache_all(void)
684 __dc_entire_op(OP_FLUSH_N_INV);
686 if (is_isa_arcv2() && !slc_data_bypass())
687 __slc_entire_op(OP_FLUSH_N_INV);
690 void flush_dcache_all(void)
692 __dc_entire_op(OP_FLUSH);
694 if (is_isa_arcv2() && !slc_data_bypass())
695 __slc_entire_op(OP_FLUSH);
699 * This is function to cleanup all caches (and therefore sync I/D caches) which
700 * can be used for cleanup before linux launch or to sync caches during
703 void sync_n_cleanup_cache_all(void)
705 __dc_entire_op(OP_FLUSH_N_INV);
708 * If SL$ is bypassed for data it is used only for instructions,
709 * and we shouldn't flush it. So invalidate it instead of flush_n_inv.
711 if (is_isa_arcv2()) {
712 if (slc_data_bypass())
713 __slc_entire_op(OP_INV);
715 __slc_entire_op(OP_FLUSH_N_INV);
718 __ic_entire_invalidate();