2 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/types.h>
11 #include <asm/byteorder.h>
16 * ARCv2 based HS38 cores are in-order issue, but still weakly ordered
17 * due to micro-arch buffering/queuing of load/store, cache hit vs. miss ...
19 * Explicit barrier provided by DMB instruction
20 * - Operand supports fine grained load/store/load+store semantics
21 * - Ensures that selected memory operation issued before it will complete
22 * before any subsequent memory operation of same type
23 * - DMB guarantees SMP as well as local barrier semantics
24 * (asm-generic/barrier.h ensures sane smp_*mb if not defined here, i.e.
25 * UP: barrier(), SMP: smp_*mb == *mb)
26 * - DSYNC provides DMB+completion_of_cache_bpu_maintenance_ops hence not needed
27 * in the general case. Plus it only provides full barrier.
30 #define mb() asm volatile("dmb 3\n" : : : "memory")
31 #define rmb() asm volatile("dmb 1\n" : : : "memory")
32 #define wmb() asm volatile("dmb 2\n" : : : "memory")
37 * ARCompact based cores (ARC700) only have SYNC instruction which is super
38 * heavy weight as it flushes the pipeline as well.
39 * There are no real SMP implementations of such cores.
42 #define mb() asm volatile("sync\n" : : : "memory")
46 #define __iormb() rmb()
47 #define __iowmb() wmb()
49 #define __iormb() asm volatile("" : : : "memory")
50 #define __iowmb() asm volatile("" : : : "memory")
53 static inline void sync(void)
55 /* Not yet implemented */
58 static inline u8 __raw_readb(const volatile void __iomem *addr)
62 __asm__ __volatile__("ldb%U1 %0, %1\n"
64 : "m" (*(volatile u8 __force *)addr)
69 static inline u16 __raw_readw(const volatile void __iomem *addr)
73 __asm__ __volatile__("ldw%U1 %0, %1\n"
75 : "m" (*(volatile u16 __force *)addr)
80 static inline u32 __raw_readl(const volatile void __iomem *addr)
84 __asm__ __volatile__("ld%U1 %0, %1\n"
86 : "m" (*(volatile u32 __force *)addr)
91 static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
93 __asm__ __volatile__("stb%U1 %0, %1\n"
95 : "r" (b), "m" (*(volatile u8 __force *)addr)
99 static inline void __raw_writew(u16 s, volatile void __iomem *addr)
101 __asm__ __volatile__("stw%U1 %0, %1\n"
103 : "r" (s), "m" (*(volatile u16 __force *)addr)
107 static inline void __raw_writel(u32 w, volatile void __iomem *addr)
109 __asm__ __volatile__("st%U1 %0, %1\n"
111 : "r" (w), "m" (*(volatile u32 __force *)addr)
115 static inline int __raw_readsb(unsigned int addr, void *data, int bytelen)
117 __asm__ __volatile__ ("1:ld.di r8, [r0]\n"
120 "stb.ab r8, [r1, 1]\n"
122 : "r" (addr), "r" (data), "r" (bytelen)
127 static inline int __raw_readsw(unsigned int addr, void *data, int wordlen)
129 __asm__ __volatile__ ("1:ld.di r8, [r0]\n"
132 "stw.ab r8, [r1, 2]\n"
134 : "r" (addr), "r" (data), "r" (wordlen)
139 static inline int __raw_readsl(unsigned int addr, void *data, int longlen)
141 __asm__ __volatile__ ("1:ld.di r8, [r0]\n"
144 "st.ab r8, [r1, 4]\n"
146 : "r" (addr), "r" (data), "r" (longlen)
151 static inline int __raw_writesb(unsigned int addr, void *data, int bytelen)
153 __asm__ __volatile__ ("1:ldb.ab r8, [r1, 1]\n"
156 "st.di r8, [r0, 0]\n"
158 : "r" (addr), "r" (data), "r" (bytelen)
163 static inline int __raw_writesw(unsigned int addr, void *data, int wordlen)
165 __asm__ __volatile__ ("1:ldw.ab r8, [r1, 2]\n"
168 "st.ab.di r8, [r0, 0]\n"
170 : "r" (addr), "r" (data), "r" (wordlen)
175 static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
177 __asm__ __volatile__ ("1:ld.ab r8, [r1, 4]\n"
180 "st.ab.di r8, [r0, 0]\n"
182 : "r" (addr), "r" (data), "r" (longlen)
188 * MMIO can also get buffered/optimized in micro-arch, so barriers needed
189 * Based on ARM model for the typical use case
192 * <writel MMIO "go" reg>
194 * <readl MMIO "status" reg>
197 * http://lkml.kernel.org/r/20150622133656.GG1583@arm.com
199 #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
200 #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
201 #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
203 #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
204 #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
205 #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
208 * Relaxed API for drivers which can handle barrier ordering themselves
210 * Also these are defined to perform little endian accesses.
211 * To provide the typical device register semantics of fixed endian,
212 * swap the byte order for Big Endian
214 * http://lkml.kernel.org/r/201603100845.30602.arnd@arndb.de
216 #define readb_relaxed(c) __raw_readb(c)
217 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
218 __raw_readw(c)); __r; })
219 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
220 __raw_readl(c)); __r; })
222 #define writeb_relaxed(v,c) __raw_writeb(v,c)
223 #define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
224 #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
226 #define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a)
227 #define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))
229 #define out_le32(a, v) out_arch(l, le32, a, v)
230 #define out_le16(a, v) out_arch(w, le16, a, v)
232 #define in_le32(a) in_arch(l, le32, a)
233 #define in_le16(a) in_arch(w, le16, a)
235 #define out_be32(a, v) out_arch(l, be32, a, v)
236 #define out_be16(a, v) out_arch(w, be16, a, v)
238 #define in_be32(a) in_arch(l, be32, a)
239 #define in_be16(a) in_arch(w, be16, a)
241 #define out_8(a, v) __raw_writeb(v, a)
242 #define in_8(a) __raw_readb(a)
245 * Clear and set bits in one shot. These macros can be used to clear and
246 * set multiple bits in a register using a single call. These macros can
247 * also be used to set a multiple-bit bit pattern using a mask, by
248 * specifying the mask in the 'clear' parameter and the new bit pattern
249 * in the 'set' parameter.
252 #define clrbits(type, addr, clear) \
253 out_##type((addr), in_##type(addr) & ~(clear))
255 #define setbits(type, addr, set) \
256 out_##type((addr), in_##type(addr) | (set))
258 #define clrsetbits(type, addr, clear, set) \
259 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
261 #define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
262 #define setbits_be32(addr, set) setbits(be32, addr, set)
263 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
265 #define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
266 #define setbits_le32(addr, set) setbits(le32, addr, set)
267 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
269 #define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
270 #define setbits_be16(addr, set) setbits(be16, addr, set)
271 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
273 #define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
274 #define setbits_le16(addr, set) setbits(le16, addr, set)
275 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
277 #define clrbits_8(addr, clear) clrbits(8, addr, clear)
278 #define setbits_8(addr, set) setbits(8, addr, set)
279 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
281 #include <asm-generic/io.h>
283 #endif /* __ASM_ARC_IO_H */