1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
9 #include <linux/types.h>
10 #include <asm/byteorder.h>
15 * ARCv2 based HS38 cores are in-order issue, but still weakly ordered
16 * due to micro-arch buffering/queuing of load/store, cache hit vs. miss ...
18 * Explicit barrier provided by DMB instruction
19 * - Operand supports fine grained load/store/load+store semantics
20 * - Ensures that selected memory operation issued before it will complete
21 * before any subsequent memory operation of same type
22 * - DMB guarantees SMP as well as local barrier semantics
23 * (asm-generic/barrier.h ensures sane smp_*mb if not defined here, i.e.
24 * UP: barrier(), SMP: smp_*mb == *mb)
25 * - DSYNC provides DMB+completion_of_cache_bpu_maintenance_ops hence not needed
26 * in the general case. Plus it only provides full barrier.
29 #define mb() asm volatile("dmb 3\n" : : : "memory")
30 #define rmb() asm volatile("dmb 1\n" : : : "memory")
31 #define wmb() asm volatile("dmb 2\n" : : : "memory")
36 * ARCompact based cores (ARC700) only have SYNC instruction which is super
37 * heavy weight as it flushes the pipeline as well.
38 * There are no real SMP implementations of such cores.
41 #define mb() asm volatile("sync\n" : : : "memory")
45 #define __iormb() rmb()
46 #define __iowmb() wmb()
48 #define __iormb() asm volatile("" : : : "memory")
49 #define __iowmb() asm volatile("" : : : "memory")
52 static inline void sync(void)
54 /* Not yet implemented */
57 static inline u8 __raw_readb(const volatile void __iomem *addr)
61 __asm__ __volatile__("ldb%U1 %0, %1\n"
63 : "m" (*(volatile u8 __force *)addr)
68 static inline u16 __raw_readw(const volatile void __iomem *addr)
72 __asm__ __volatile__("ldw%U1 %0, %1\n"
74 : "m" (*(volatile u16 __force *)addr)
79 static inline u32 __raw_readl(const volatile void __iomem *addr)
83 __asm__ __volatile__("ld%U1 %0, %1\n"
85 : "m" (*(volatile u32 __force *)addr)
90 static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
92 __asm__ __volatile__("stb%U1 %0, %1\n"
94 : "r" (b), "m" (*(volatile u8 __force *)addr)
98 static inline void __raw_writew(u16 s, volatile void __iomem *addr)
100 __asm__ __volatile__("stw%U1 %0, %1\n"
102 : "r" (s), "m" (*(volatile u16 __force *)addr)
106 static inline void __raw_writel(u32 w, volatile void __iomem *addr)
108 __asm__ __volatile__("st%U1 %0, %1\n"
110 : "r" (w), "m" (*(volatile u32 __force *)addr)
114 static inline int __raw_readsb(unsigned int addr, void *data, int bytelen)
116 __asm__ __volatile__ ("1:ld.di r8, [r0]\n"
119 "stb.ab r8, [r1, 1]\n"
121 : "r" (addr), "r" (data), "r" (bytelen)
126 static inline int __raw_readsw(unsigned int addr, void *data, int wordlen)
128 __asm__ __volatile__ ("1:ld.di r8, [r0]\n"
131 "stw.ab r8, [r1, 2]\n"
133 : "r" (addr), "r" (data), "r" (wordlen)
138 static inline int __raw_readsl(unsigned int addr, void *data, int longlen)
140 __asm__ __volatile__ ("1:ld.di r8, [r0]\n"
143 "st.ab r8, [r1, 4]\n"
145 : "r" (addr), "r" (data), "r" (longlen)
150 static inline int __raw_writesb(unsigned int addr, void *data, int bytelen)
152 __asm__ __volatile__ ("1:ldb.ab r8, [r1, 1]\n"
155 "st.di r8, [r0, 0]\n"
157 : "r" (addr), "r" (data), "r" (bytelen)
162 static inline int __raw_writesw(unsigned int addr, void *data, int wordlen)
164 __asm__ __volatile__ ("1:ldw.ab r8, [r1, 2]\n"
167 "st.ab.di r8, [r0, 0]\n"
169 : "r" (addr), "r" (data), "r" (wordlen)
174 static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
176 __asm__ __volatile__ ("1:ld.ab r8, [r1, 4]\n"
179 "st.ab.di r8, [r0, 0]\n"
181 : "r" (addr), "r" (data), "r" (longlen)
187 * MMIO can also get buffered/optimized in micro-arch, so barriers needed
188 * Based on ARM model for the typical use case
191 * <writel MMIO "go" reg>
193 * <readl MMIO "status" reg>
196 * http://lkml.kernel.org/r/20150622133656.GG1583@arm.com
198 #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
199 #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
200 #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
202 #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
203 #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
204 #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
207 * Relaxed API for drivers which can handle barrier ordering themselves
209 * Also these are defined to perform little endian accesses.
210 * To provide the typical device register semantics of fixed endian,
211 * swap the byte order for Big Endian
213 * http://lkml.kernel.org/r/201603100845.30602.arnd@arndb.de
215 #define readb_relaxed(c) __raw_readb(c)
216 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
217 __raw_readw(c)); __r; })
218 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
219 __raw_readl(c)); __r; })
221 #define writeb_relaxed(v,c) __raw_writeb(v,c)
222 #define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
223 #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
225 #define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a)
226 #define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))
228 #define out_le32(a, v) out_arch(l, le32, a, v)
229 #define out_le16(a, v) out_arch(w, le16, a, v)
231 #define in_le32(a) in_arch(l, le32, a)
232 #define in_le16(a) in_arch(w, le16, a)
234 #define out_be32(a, v) out_arch(l, be32, a, v)
235 #define out_be16(a, v) out_arch(w, be16, a, v)
237 #define in_be32(a) in_arch(l, be32, a)
238 #define in_be16(a) in_arch(w, be16, a)
240 #define out_8(a, v) __raw_writeb(v, a)
241 #define in_8(a) __raw_readb(a)
244 * Clear and set bits in one shot. These macros can be used to clear and
245 * set multiple bits in a register using a single call. These macros can
246 * also be used to set a multiple-bit bit pattern using a mask, by
247 * specifying the mask in the 'clear' parameter and the new bit pattern
248 * in the 'set' parameter.
251 #define clrbits(type, addr, clear) \
252 out_##type((addr), in_##type(addr) & ~(clear))
254 #define setbits(type, addr, set) \
255 out_##type((addr), in_##type(addr) | (set))
257 #define clrsetbits(type, addr, clear, set) \
258 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
260 #define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
261 #define setbits_be32(addr, set) setbits(be32, addr, set)
262 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
264 #define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
265 #define setbits_le32(addr, set) setbits(le32, addr, set)
266 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
268 #define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
269 #define setbits_be16(addr, set) setbits(be16, addr, set)
270 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
272 #define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
273 #define setbits_le16(addr, set) setbits(le16, addr, set)
274 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
276 #define clrbits_8(addr, clear) clrbits(8, addr, clear)
277 #define setbits_8(addr, set) setbits(8, addr, set)
278 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
280 #include <asm-generic/io.h>
282 #endif /* __ASM_ARC_IO_H */