arch/arc/dts/axs10x_mb.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
   4  */
   5
   6 / {
   7         aliases {
   8                 spi0 = &spi0;
   9         };
  10
  11         axs10x_mb@e0000000 {
  12                 compatible = "simple-bus";
  13                 #address-cells = <1>;
  14                 #size-cells = <1>;
  15                 ranges = <0x00000000 0xe0000000 0x10000000>;
  16                 u-boot,dm-pre-reloc;
  17
  18                 clocks {
  19                         compatible = "simple-bus";
  20                         u-boot,dm-pre-reloc;
  21
  22                         apbclk: apbclk {
  23                                 compatible = "fixed-clock";
  24                                 clock-frequency = <50000000>;
  25                                 #clock-cells = <0>;
  26                         };
  27
  28                         uartclk: uartclk {
  29                                 compatible = "fixed-clock";
  30                                 clock-frequency = <33333333>;
  31                                 #clock-cells = <0>;
  32                                 u-boot,dm-pre-reloc;
  33                         };
  34                 };
  35
  36                 ethernet@18000 {
  37                         compatible = "altr,socfpga-stmmac";
  38                         reg = < 0x18000 0x2000 >;
  39                         phy-mode = "gmii";
  40                         snps,pbl = < 32 >;
  41                         clocks = <&apbclk>;
  42                         clock-names = "stmmaceth";
  43                         max-speed = <100>;
  44                 };
  45
  46                 ehci@0x40000 {
  47                         compatible = "generic-ehci";
  48                         reg = < 0x40000 0x100 >;
  49                 };
  50
  51                 ohci@0x60000 {
  52                         compatible = "generic-ohci";
  53                         reg = < 0x60000 0x100 >;
  54                 };
  55
  56                 uart0: serial0@22000 {
  57                         compatible = "snps,dw-apb-uart";
  58                         reg = <0x22000 0x100>;
  59                         clocks = <&uartclk>;
  60                         reg-shift = <2>;
  61                         reg-io-width = <4>;
  62                 };
  63
  64                 spi0: spi@0 {
  65                         compatible = "snps,dw-apb-ssi";
  66                         reg = <0x0 0x100>;
  67                         #address-cells = <1>;
  68                         #size-cells = <0>;
  69                         spi-max-frequency = <4000000>;
  70                         clocks = <&apbclk>;
  71                         clock-names = "spi_clk";
  72                         cs-gpio = <&cs_gpio 0>;
  73                         spi_flash@0 {
  74                                 compatible = "spi-flash";
  75                                 reg = <0>;
  76                                 spi-max-frequency = <4000000>;
  77                         };
  78                 };
  79
  80                 cs_gpio: gpio@11218 {
  81                         compatible = "snps,creg-gpio";
  82                         reg = <0x11218 0x4>;
  83                         gpio-controller;
  84                         #gpio-cells = <1>;
  85                         gpio-bank-name = "axs-spi-cs";
  86                         gpio-count = <1>;
  87                         gpio-first-shift = <0>;
  88                         gpio-bit-per-line = <2>;
  89                         gpio-activate-val = <1>;
  90                         gpio-deactivate-val = <3>;
  91                         gpio-default-val = <1>;
  92                 };
  93         };
  94 };