1 menu "ARC architecture"
11 prompt "CPU selection"
18 Choose this option to build an U-Boot for ARC750D CPU.
24 Choose this option to build an U-Boot for ARC770D CPU.
30 default ARC_MMU_V3 if CPU_ARC770D
31 default ARC_MMU_V2 if CPU_ARC750D
35 depends on CPU_ARC750D
37 Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
38 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
42 depends on CPU_ARC770D
44 Introduced with ARC700 4.10: New Features
45 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
46 Shared Address Spaces (SASID)
51 bool "Enable Big Endian Mode"
54 Build kernel for Big Endian Mode of ARC CPU
57 bool "Do not use Instruction Cache"
61 bool "Do not use Data Cache"
64 config ARC_CACHE_LINE_SHIFT
65 int "Cache Line Length (as power of 2)"
68 depends on !SYS_DCACHE_OFF || !SYS_DCACHE_OFF
70 Starting with ARC700 4.9, Cache line length is configurable,
71 This option specifies "N", with Line-len = 2 power N
72 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
73 Linux only supports same line lengths for I and D caches.
76 prompt "Target select"
81 config TARGET_ARCANGEL4
82 bool "Support arcangel4"
89 source "board/abilis/tb100/Kconfig"
90 source "board/synopsys/Kconfig"
91 source "board/synopsys/axs101/Kconfig"