Linux-libre 5.3.12-gnu
[librecmc/linux-libre.git] / Documentation / devicetree / bindings / spi / spi-pl022.yaml
1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-pl022.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: ARM PL022 SPI controller
8
9 maintainers:
10   - Linus Walleij <linus.walleij@linaro.org>
11
12 allOf:
13   - $ref: "spi-controller.yaml#"
14
15 # We need a select here so we don't match all nodes with 'arm,primecell'
16 select:
17   properties:
18     compatible:
19       contains:
20         const: arm,pl022
21   required:
22     - compatible
23
24 properties:
25   compatible:
26     items:
27       - const: arm,pl022
28       - const: arm,primecell
29
30   reg:
31     maxItems: 1
32
33   interrupts:
34     maxItems: 1
35
36   clocks:
37     maxItems: 2
38
39   clock-names:
40     items:
41       - enum:
42           - SSPCLK
43           - sspclk
44       - const: apb_pclk
45
46   pl022,autosuspend-delay:
47     description: delay in ms following transfer completion before the
48       runtime power management system suspends the device. A setting of 0
49       indicates no delay and the device will be suspended immediately.
50     $ref: "/schemas/types.yaml#/definitions/uint32"
51
52   pl022,rt:
53     description: indicates the controller should run the message pump with realtime
54                priority to minimise the transfer latency on the bus (boolean)
55     type: boolean
56
57   dmas:
58     description:
59       Two or more DMA channel specifiers following the convention outlined
60       in bindings/dma/dma.txt
61     minItems: 2
62     maxItems: 32
63
64   dma-names:
65     description:
66       There must be at least one channel named "tx" for transmit and named "rx"
67       for receive.
68     minItems: 2
69     maxItems: 32
70     additionalItems: true
71     items:
72       - const: rx
73       - const: tx
74
75 patternProperties:
76   "^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-f]+$":
77     type: object
78     # SPI slave nodes must be children of the SPI master node and can
79     # contain the following properties.
80     properties:
81       pl022,interface:
82         description: SPI interface type
83         allOf:
84           - $ref: "/schemas/types.yaml#/definitions/uint32"
85           - enum:
86               - 0  # SPI
87               - 1  # Texas Instruments Synchronous Serial Frame Format
88               - 2  # Microwire (Half Duplex)
89
90       pl022,com-mode:
91         description: Specifies the transfer mode
92         allOf:
93           - $ref: "/schemas/types.yaml#/definitions/uint32"
94           - enum:
95               - 0  # interrupt mode
96               - 1  # polling mode
97               - 2  # DMA mode
98             default: 1
99
100       pl022,rx-level-trig:
101         description: Rx FIFO watermark level
102         allOf:
103           - $ref: "/schemas/types.yaml#/definitions/uint32"
104           - minimum: 0
105             maximum: 4
106
107       pl022,tx-level-trig:
108         description: Tx FIFO watermark level
109         allOf:
110           - $ref: "/schemas/types.yaml#/definitions/uint32"
111           - minimum: 0
112             maximum: 4
113
114       pl022,ctrl-len:
115         description: Microwire interface - Control length
116         allOf:
117           - $ref: "/schemas/types.yaml#/definitions/uint32"
118           - minimum: 0x03
119             maximum: 0x1f
120
121       pl022,wait-state:
122         description: Microwire interface - Wait state
123         allOf:
124           - $ref: "/schemas/types.yaml#/definitions/uint32"
125           - enum: [ 0, 1 ]
126
127       pl022,duplex:
128         description: Microwire interface - Full/Half duplex
129         allOf:
130           - $ref: "/schemas/types.yaml#/definitions/uint32"
131           - enum: [ 0, 1 ]
132
133 required:
134   - compatible
135   - reg
136   - interrupts
137
138 examples:
139   - |
140     spi@e0100000 {
141       compatible = "arm,pl022", "arm,primecell";
142       reg = <0xe0100000 0x1000>;
143       #address-cells = <1>;
144       #size-cells = <0>;
145       interrupts = <0 31 0x4>;
146       dmas = <&dma_controller 23 1>,
147         <&dma_controller 24 0>;
148       dma-names = "rx", "tx";
149
150       m25p80@1 {
151         compatible = "st,m25p80";
152         reg = <1>;
153         spi-max-frequency = <12000000>;
154         spi-cpol;
155         spi-cpha;
156         pl022,interface = <0>;
157         pl022,com-mode = <0x2>;
158         pl022,rx-level-trig = <0>;
159         pl022,tx-level-trig = <0>;
160         pl022,ctrl-len = <0x11>;
161         pl022,wait-state = <0>;
162         pl022,duplex = <0>;
163       };
164     };
165 ...