2 -----------------------
5 - compatible: cdns,sierra-phy-t0
6 - clocks: Must contain an entry in clock-names.
7 See ../clocks/clock-bindings.txt for details.
8 - clock-names: Must be "phy_clk"
9 - resets: Must contain an entry for each in reset-names.
10 See ../reset/reset.txt for details.
11 - reset-names: Must include "sierra_reset" and "sierra_apb".
12 "sierra_reset" must control the reset line to the PHY.
13 "sierra_apb" must control the reset line to the APB PHY
15 - reg: register range for the PHY.
16 - #address-cells: Must be 1
17 - #size-cells: Must be 0
20 - cdns,autoconf: A boolean property whose presence indicates that the
21 PHY registers will be configured by hardware. If not
22 present, all sub-node optional properties must be
26 Each group of PHY lanes with a single master lane should be represented as
27 a sub-node. Note that the actual configuration of each lane is determined by
28 hardware strapping, and must match the configuration specified here.
30 Sub-node required properties:
31 - #phy-cells: Generic PHY binding; must be 0.
32 - reg: The master lane number. This is the lowest numbered lane
34 - resets: Must contain one entry which controls the reset line for the
35 master lane of the sub-node.
36 See ../reset/reset.txt for details.
38 Sub-node optional properties:
39 - cdns,num-lanes: Number of lanes in this group. From 1 to 4. The
40 group is made up of consecutive lanes.
41 - cdns,phy-type: Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on
42 configuration of lanes.
45 pcie_phy4: pcie-phy@fd240000 {
46 compatible = "cdns,sierra-phy-t0";
47 reg = <0x0 0xfd240000 0x0 0x40000>;
48 resets = <&phyrst 0>, <&phyrst 1>;
49 reset-names = "sierra_reset", "sierra_apb";
51 clock-names = "phy_clk";
54 pcie0_phy0: pcie-phy@0 {
59 cdns,phy-type = <PHY_TYPE_PCIE>;
61 pcie0_phy1: pcie-phy@2 {
66 cdns,phy-type = <PHY_TYPE_PCIE>;