1 Qualcomm adreno/snapdragon GMU (Graphics management unit)
3 The GMU is a programmable power controller for the GPU. the CPU controls the
4 GMU which in turn handles power controls for the GPU.
7 - compatible: "qcom,adreno-gmu-XYZ.W", "qcom,adreno-gmu"
8 for example: "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"
9 Note that you need to list the less specific "qcom,adreno-gmu"
10 for generic matches and the more specific identifier to identify
12 - reg: Physical base address and length of the GMU registers.
13 - reg-names: Matching names for the register regions
17 - interrupts: The interrupt signals from the GMU.
18 - interrupt-names: Matching names for the interrupts
21 - clocks: phandles to the device clocks
22 - clock-names: Matching names for the clocks
27 - power-domains: should be:
28 <&clock_gpucc GPU_CX_GDSC>
29 <&clock_gpucc GPU_GX_GDSC>
30 - power-domain-names: Matching names for the power domains
31 - iommus: phandle to the adreno iommu
32 - operating-points-v2: phandle to the OPP operating points
40 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
42 reg = <0x506a000 0x30000>,
45 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
47 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
48 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
49 interrupt-names = "hfi", "gmu";
51 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
52 <&gpucc GPU_CC_CXO_CLK>,
53 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
54 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
55 clock-names = "gmu", "cxo", "axi", "memnoc";
57 power-domains = <&gpucc GPU_CX_GDSC>,
59 power-domain-names = "cx", "gx";
61 iommus = <&adreno_smmu 5>;
63 operating-points-v2 = <&gmu_opp_table>;