1 Allwinner Memory Bus (MBUS) controller
3 The MBUS controller drives the MBUS that other devices in the SoC will
4 use to perform DMA. It also has a register interface that allows to
5 monitor and control the bandwidth and priorities for masters on that
9 - compatible: Must be one of:
10 - allwinner,sun5i-a13-mbus
11 - reg: Offset and length of the register set for the controller
12 - clocks: phandle to the clock driving the controller
13 - dma-ranges: See section 2.3.9 of the DeviceTree Specification
14 - #interconnect-cells: Must be one, with the argument being the MBUS
17 Each device having to perform their DMA through the MBUS must have the
18 interconnects and interconnect-names properties set to the MBUS
19 controller and with "dma-mem" as the interconnect name.
23 mbus: dram-controller@1c01000 {
24 compatible = "allwinner,sun5i-a13-mbus";
25 reg = <0x01c01000 0x1000>;
26 clocks = <&ccu CLK_MBUS>;
27 dma-ranges = <0x00000000 0x40000000 0x20000000>;
28 #interconnect-cells = <1>;
31 fe0: display-frontend@1e00000 {
32 compatible = "allwinner,sun5i-a13-display-frontend";
34 interconnects = <&mbus 19>;
35 interconnect-names = "dma-mem";